• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.598-601
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• 2006

The radio signal in GNSS was intentionally designed with two frequencies in order to combat the dispersion error caused by trans-ionospheric propagation. By measuring the path delay independently at the two, widely spaced GPS frequencies, L1 & L2, the TEC along the path from satellite to receiver can be measured directly. The issue with dual frequency measurement of the ionosphere is the calibration of L1/L2 interfrequency biases. L1/L2 interfrequency biases are generated because physical electric signal paths of L1 and L2 circuits are different from each other for both satellites and receiver. Conventionally L1/L2 interfrequency bias is estimated and broadcasted by 2D ionospheric model. In this paper, we estimated IFB (interfrequency bias) by 2D & 3D ionospheric models including real time filter methods and compared the result of those and concluded the merit of 3D tomography model to recover the problem of 2D thin shell model. We confirmed our conclusion by experimental data.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.9
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• pp.1802-1808
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• 2009

A fault detection observer with finite time convergence characteristics(FT_FDO) is proposed and applied to a fault detection isolation system for a dynamic control system. The FT_FDO is a kind of dual state-observer scheme that provides with the state estimates insensitive to a specified fault and the corresponding fault estimate. The state estimates are processed to get the residual that will be logically compared with other residuals to detect and isolate the fault of interest, and the fault estimate may be used for fault compensation. The FDIS employing the FT_FDOs can be considered to be a multiple observer schemes(MOS) in which FT_FDOs are parallelly driven to generate a set of residuals to be compared each other. Due to the finite time convergence characteristics of the FT_FDO, the predetermined detection delay can be considered in the design stage of FDIS so that any fault of interest can be detected and identified in that time. It evidently resolves a well known difficulty of threshold selection owing to the transient responses of the fault detection observers(FDO) employed in FDIS. An FDIS is constructed for instruments(2-sensor, 1-actuator) in an inverted pendulum control system, and simulations are performed to show the performance of the FDIS and fault tolerant control system.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.1
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• pp.1-9
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• 2017

With the Development of Wireless Network Technology and Wireless Link Technology, Wireless Mesh Network (WMN) is Attracting Attention as a Key Technology to Construct the Wireless Transit Network. The WMN has been Studied for a Long Time in Various Fields, however there are still many Problems that have not been solved yet. One of them is the Routing Problem to find an Optimal path in a Multi-hop Network Composed of Wireless Links. In the Hybrid-WMN, which is one of the Three Types of WMN, Optimal Path Selection Requires Research on Path Search Protocols that Effectively use the Infrastructure Mesh as a Transit Network, Together with Research for a Routing Metric with Excellent Performance. Therefore, this Paper Proposes a Dual Mode-AODV(Ad hoc On-demand Distance Vector) for Hybrid-WMN. Simulation result shows that the Path Selection Delay was Reduced by 52% than AODV when the Proposed Dual Mode-AODV was applied.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11B
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• pp.1178-1190
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• 2009

IEEE 802.11e proposed by IEEE 802.11 working group to guarantee QoS has contention based EDCA and contention free based HCCA. HCCA, a centralized polling based mechanism of 802.11e, needs a scheduling algorithm to allocate the network resource efficiently. The existing standard scheduler, however, is inefficient to support for QoS guarantee for real-time service having VBR traffic. To efficiently assign resource for VBR traffic, in this paper, we propose TXOP algorithm based on dual leaky bucket using average resource allocation and peak resource allocation. The minimum TXOP of each station is obtained by using statistical approach to maximize number of stations of which performance satisfy QoS target. Simulation results show that the proposed algorithm has much higher performance compared with reference scheduler in terms of throughput and delay.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.10
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• pp.573-581
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• 2002

In this paper, we propose a mediaprocessor of dual-cache architecture which is composed of the multimedia data cache and the general-purpose data cache to prevent performance degradation caused by memory delay. In the proposed processor architecture, multimedia data that are written in subword instructions are loaded in the multimedia data cache and the remaining data are loaded in the general-purpose data cache. Also, Ive use multi-block prefetching scheme that fetches two consecutive data blocks into a cache at a time to exploit the locality of multimedia data. Experimental results on MPEG and JPEG benchmark programs show that the proposed processor architecture results in better performance than the processor equipped with single data cache.

• Journal of the Korean Institute of Gas
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• v.19 no.6
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• pp.28-33
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• 2015

In this study, a dual fuel engine fueled with natural gas and diesel was tested to investigate the effects of heating value variation of CNG fuel. CNG substitution rate which is defined as the ratio of CNG and diesel supplied in a heating value basis was fixed at 80%. The higher heating value was varied from $10,400kcal/Nm^3$ to $9,400kcal/Nm^3$ by mixing nitrogen gas with pure CNG and diesel fuel was injected at a fixed injection timing. The engine test results showed that thermal efficiency and power output were decreased as the heating value of mixed CNG fuel was decreased. And the peak cylinder pressure was also decreased but the ignition delay time and the combustion duration and timing were almost same.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.717-720
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• 2000

Event-driven communication protocols such as CAN(Controller Area Network) have inherent packet delays due to the contention process for the use of network medium. These delays are stochastic in nature because most packets arrive at random time instants. The stochastic property of the delay adversely influences the control system's performance in terms of stability, responsiveness and steady-state error. Another problem for safety-critical application such as brake-by-wire systems is the reliability of the communication modules that can fail abruptly. This paper deals with two methods to overcome the above problems : (i) scheduling method that can maintain packet delays under some acceptable level, and (ii) redundancy management of communication modules that prescribes dual-redundancy modules' behavior when one of them fails.