• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.1149-1152
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• 1999

In this paper we analyzed each region of specific points and ｅ-Δｅphase plane in order to make fuzzy rule base. After we composed the fuzzy control rules which can decrease rise time, delay time, maximum overshoot than basic fuzzy control rules. The composed method are converged more rapidly than single rule base in convergence region. Proposed method is alternately use at specific points of ｅ-Δｅphase plane with two fuzzy control rules, that is one control rule occruing the steady state error used in transient region and another fuzzy control rule use to decrease the steady state error and rapidly converge at the convergence region. Two fuzzy control rules in the ｅ-Δｅ phase plane decide the change time according to response characteristics of plants. As the results of simulation through the second order plant and the delay time plan, Proposed dual fuzzy control rules get the good response compare with the basic fuzzy control rule.

• 전기전자학회논문지
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• 제20권2호
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• pp.167-170
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• 2016

정적 램의 비트라인을 정밀하게 추적하는 감지증폭기의 enable 신호를 만들기 위해 replica bit-line 기술 (RBL)이 사용된다. 하지만, 공정으로 인한 문턱전압의 변화는 replica bit-line 회로에 흐르는 전류를 변화시키고 이는 감지증폭기의 enable 신호 생성 시간 ($T_{SAE}$)을 변화시키며, 결과적으로는 읽기 동작을 불안정하게 한다. 본 논문에서는 conventional replica bit-line delay ($RBL_{conv}$)구조 및 $T_{SAE}$ 변화를 감소시킬 수 있는 개선 구조인 dual replica bit-line delay (DRBD)구조와 multi-stage dual replica bit-line delay(MDRBD)구조를 소개하고, 14nm FinFET 공정, 동작전압 0.6V에서 각 기술들에 대한 읽기 성공률이 $6{\sigma}$를 만족하는 최대 on-cell 개수를 simulation을 통해 찾고 이때 각 구조에 대한 performance와 에너지를 비교했다. 그 결과, $RBL_{conv}$ 대비 DRBD와 MDRBD의 performance는 각각 24.4%와 48.3% 저하되고 에너지 소모는 각각 8%와 32.4% 감소된 것을 관찰하였다.

• Journal of Power Electronics
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• 제16권4호
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• pp.1565-1577
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• 2016

For grid-connected LCL-filtered inverters, dual-loop current control with an inner-loop active damping (AD) based on capacitor current feedback is generally used for the sake of current quality. However, existing studies on capacitor current feedback AD with a control delay do not reveal the mathematical relation among the dual-loop stability, capacitor current feedback factor, delay time and LCL parameters. The robustness was not investigated through mathematical derivations. Thus, this paper aims to provide a systematic study of dual-loop current control in a digitally-controlled inverter. At first, the stable region of the inner-loop AD is derived. Then, the dual-loop stability and robustness are analyzed by mathematical derivations when the inner-loop AD is stable and unstable. Robust design principles for the inner-loop AD feedback factor and the outer-loop current controller are derived. Most importantly, ensuring the stability of the inner-loop AD is critical for achieving high robustness against a large grid impedance. Then, several improved approaches are proposed and synthesized. The limitations and benefits of all of the approaches are identified to help engineers apply capacitor current feedback AD in practice.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.423-427
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• 1993

A velocity planning method is proposed that ensures collision-free and minimal delay-time motions for two robotic manipulators and auxiliary equipments. Additional path, which makes robot start with possible largest speed, is added to the original prescribed path of one of two robots, and this running start along the additional path reduces delay time introduced to avoid collision between the robots and therefore reduces total traveling time.

• 한국산업융합학회 논문집
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• 제27권4_2호
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• pp.935-942
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• 2024

This study analyzes the effects of the parasitic capacitance of the SiC MOSFET used in the Dual Active Bridge ( DAB) converter and proposes a method for calculating the leakage inductance of the transformer. The DAB converter employs high-frequency switching to achieve high efficiency, high power density, and reliability. MOSFETs possess parasitic capacitance, which induces resonance with the leakage inductance of the transformer during switching operations, resulting in a voltage change delay. This paper discusses the effect of the delay of voltage changes on the DAB converter output and proposes a method to calculate the delay time. This method aims to equalize the delay time to minimize this effect and enhance the accuracy of the leakage inductance calculation of the transformer. The proposed method is validated through experiments and simulations.

• 정보처리학회논문지A
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• 제10A권3호
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• pp.247-254
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• 2003

본 연구에서 고속 데이터 전송을 위해 Double Data Rate(DDR) 방식을 사용하는 SDRAM에 내장할 수 있는 저전압 광대역 Delay Locked Loop(DLL) 회로를 설계하였다. 고해상도와 빠른 Lock-on 시간을 위하여 새로운 유형의 위상검출기론 설계하였고 카운터 및 Indicator 등 내장회로의 빠른 동작을 위해 Dual-Data Dual-Clock 플립플롭(DCDD FF)에 기반을 둔 설계를 수행하였으며 이 FF을 사용하므로서 소자수를 70% 정도 감소시킬 수 있었다. Delay Line 중에서 Coarse 부분은 0.2ns 이하까지 검출 가능하며 위상오차를 더욱 감소시키고 빠른 Lock-on 기간을 얻기 위해 Fine 부분에 3-step Vernier Line을 설계하였다. 이 방식을 사용한 본 DLL의 위상오차는 매우 적고 25ps 정도이다. 본 DLL의 Locking 범위는 50∼500MHz로 넓으며 5 클럭 이내의 빠른 Locking을 얻을 수 있다. 0.25um CMOS 공정에서 1.8V 공급전압 사용시 소비전류는 500MHZ 주파수에서 32mA이다. 본 DLL은 고주파 통신 시스템의 동기화와 같은 다른 응용면에도 이용할 수 있다.

• Journal of Positioning, Navigation, and Timing
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• 제12권2호
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• pp.141-148
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• 2023

In this paper, impacts of tropospheric delay gradient correction on PPP positioning performance were analyzed. A correction for tropospheric delay error due to the gradient was created and applied using external data, and reference station data were collected on a sunny day and a rainy day to analyze the GPS only dual-frequency PPP positioning results. As a result, on the sunny day, the convergence time was about 35 minutes and the final 3D position error was 10 cm, regardless of whether the correction for the tropospheric delay error by the gradient was applied. On the other hand, on the rainy day, the 3D position error converges only when the correction was applied, and the convergence time was about 34 minutes. Furthermore, the final 3D position error was improved from 30 cm to 10 cm. In addition, the analysis of the PPP by reference station location on the rainy day showed that the PPP positioning performance was improved when the correction was applied to a user located in an area where the weather changes.

• 한국군사과학기술학회지
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• 제20권3호
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• pp.413-420
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• 2017

We investigate the performance of a true time delay(TTD) phase shifter to reduce the beam squint caused by frequency changes of a phased array antenna in wideband communication systems. To design a high gain phased array antenna, we need a long TTD, which causes high RF loss, low resolution and large dimension of TTD phase shifters. To overcome the problems, we propose a schematic of dual TTD phase shifters, which consists of short time delay(STD) in radio frequency(RF) part and long time delay(LTD) in intermediate frequency(IF) part. Our analysis results show that the proposed scheme reduces the required bits and delay time in RF band of the TTD compared to the conventional single TTD scheme.

• Journal of the Optical Society of Korea
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• 제20권2호
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• pp.300-304
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• 2016

A dual loop optoelectronic oscillator (OEO) based on an acousto-optic modulator (AOM) for single mode operation with an acousto-optic delay line is demonstrated in this paper. When the OEO operates, the free spectral range is a function of the total loop length of the OEO, which is mainly dependent on the propagation time of the acoustic wave in the AOM. Due to the huge difference in the magnitude between the speed of light and the acoustic velocity in the AOM, the effective loop length converted to light-propagation length of the OEO increases to 3.8 km. With 150 MHz oscillation frequency, phase noise of -118 dBc/Hz at 10 kHz frequency offset, and -140 dBc/Hz at 200 kHz frequency offset, is achieved.

• 전자공학회논문지SC
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• 제44권1호
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• pp.74-84
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• 2007

본 논문에서는 기존의 DLL 지연 시간 잠금 범위를 확장하기 위해 새로운 이중 루프 DLL을 제안하였다. 제안한 DLL은 Coarse_loop와 Fine_loop를 포함하고 있으며, 와부 클럭과 2개의 내부 클럭 사이의 초기 시간차를 비교하여 하나의 루프를 선택하여 동작하게 된다. 2개의 내부 클럭은 VCDL의 중간 출력 클럭과 최종 출력 클럭이며 두 클럭의 위상차는 $180^{\circ}$이다. 제안한 DLL은 일반적인 잠금 범위 밖에 있을 경우 Coarse_loop를 선택하여 잠금 범위 안으로 이전 시킨 후 Fine_loop에 의하여 잠금 상태가 일어난다. 따라서 제안한 DLL은 harmonic lock이 일어나지 않는 한 항상 안정적으로 잠금 과정이 일어날 수 있게 된다. 제안한 DLL이 사용하는 VCDL은 두 개의 제어 전압을 받아 지연 시간을 조절함으로 일반적인 다 적층 currentstarved 형태의 인버터 대신에 TG 트랜지스터를 이용하는 인버터를 사용하여 지연 셀을 구성하였다. 새로운 VCDL은 종래의 VCDL에 비하여 지연시간 범위가 더욱 확장되었으며, 따라서 제안한 DLL의 잠금 범위는 기존의 DLL의 잠금 범위보다 2배 이상 확장되었다. 본 논문에서 제안한 DLL 회로는 0.18um, 1.8V TSMC CMOS 라이브러리를 기본으로 하여 설계, 시뮬레이션 및 검증하였으며 동작 주파수 범위가 100MHz${\sim}$1GHz이다. 또한, 1GHz에서 제안한 DLL의 잠금 상태에서의 최대 위상 오차는 11.2ps로 높은 해상도를 가졌으며, 이때 소비 전력은 11.5mW로 측정되었다.