• Journal of Power Electronics
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• v.16 no.3
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• pp.1036-1045
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• 2016

This paper presents a novel control strategy for passive output filter reduction using an active output filter. The proposed method achieves the dual-function of regulating the output voltage ripple and output voltage variation during load transients. The novel control strategy allows traditional simple voltage controllers to be used, without requiring the expensive current sensors and complex controllers used in conventional approaches. The proposed method is verified with results from a 125-W forward converter.

• Journal of IKEEE
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• v.26 no.2
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• pp.271-279
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• 2022

This paper proposes an advanced dead-time compensation method for dual inverter with a floating capacitor. The dual inverter with floating capacitor is composed of double two-level inverters and a bulk electrolytic capacitor. The output voltage of the dual inverter is dropped by the conduction voltage of the power semiconductors. The voltage drop and dead-time cause the fundamental and harmonic distortions of output currents. When supplied power for OEW-load is low, the dual inverter operates as single inverter for effective operation. The dead-time compensation method for the dual inverter operated as single inverter is needed for reliability. The proposed method using band pass filter in this paper compensates dead-time, dead-time error and changed voltage drop error of power semiconductors for the dual inverter and dual inverter operated as single inverter. The effectiveness of the proposed method is verified by simulation results.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.129-131
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• 2006

This paper presents a new ZVS-PWM high frequency inverter. The ZVS operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. The operating principle and the operating characteristics of the new high frequency circuit treated here are illustrated and evaluated on the basis of simulation results. It was examined that the complete soft switching operation can be achieved even for low power setting ranges by introducing the high frequency dual duty cycle control scheme. In the proposed high frequency inverter treated here, the dual mode pulse modulation control strategy of the asymmetrical PWM in the higher power setting ranges and the lower power setting ones, the output power of this high frequency inverter could introduce in order to extend soft switching operation ranges. Dual duty cycle is used to provide a wide range of output power regulation that is important in many high frequency inverter applications. It is more suitable for induction heating applications the operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

• Journal of electromagnetic engineering and science
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• v.13 no.2
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• pp.93-103
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• 2013

This paper presented a novel approach for the design of a tunable dual-band bandpass filter (BPF) with independently tunable passband center frequencies and bandwidths. The newly proposed dual-band filter principally comprised two dual-mode single band filters using common input/output lines. Each single BPF was realized using a varactor-loaded transmission line resonator. To suppress the harmonics over a broad bandwidth, a defected ground structure was used at the input/output feeding lines. From the experimental results, it was found that the proposed filter exhibited the first passband center frequency tunable range from 1.48 to 1.8 GHz with a 3-dB fractional bandwidth (FBW) variation from 5.76% to 8.55%, while the second passband center's frequency tunable range was 2.40 to 2.88 GHz with a 3-dB FBW variation from 8.28% to 12.42%. The measured results of the proposed filters showed a rejection level of 19 dB up to more than 10 times the highest center frequency of the first passband.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.423-430
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.376-379
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• 2014

In this paper, we designed more improving a dual-band power amplifier than the transceiver of RFID reader that operates at 910 MHz and 2.45 GHz. A dual-band power amplifier has two circuits. One matching circuit is composed lumped element in the band of 910 MHz. The other matching circuit using distributed element in the high band of 2.45 GHz. So, this dual-band power amplifier works as Band Rejection Filter in the band of 910 MHz but in the high band of 2.45 GHz works as Band Pass Filter. Therefore, this is composed a microstrip transmission line. A power amplifier is showed gains of 8 dB output power at 910 MHz and 1.5 dB output power at 2.45 GHz. If input power is 10 dBm, both of bands output 20 dBm.

• Journal of Welding and Joining
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• v.26 no.2
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• pp.85-91
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• 2008

In general, the quality of a welding process tends to vary with depending on the work environment or external disturbances. Hence, in order to achieve the desirable quality of welding, we should have the optimal welding condition that is not significantly affected by these changes in the environment or external disturbances. In this study, we used a dual response surface method in consideration of both the mean output variables and the standard deviation in order to optimize the V-groove arc welding process. The input variables for GMA welding process with the dual response surface are welding voltage, welding current and welding speed. The output variables are the welding quality function using the shape factor of bead geometry. First, we performed welding experiment on the interested area according to the central composite design. From the results obtained, we derived the regression model on the mean and standard deviation between the input and output variables of the welding process and then obtained the dual response surface. Finally, using the grid search method, we obtained the input variables that minimize the object function which led to the optimal V-groove arc welding process.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.56-61
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• 2010

In this paper, high efficient power amplifier with dual band has been realized. Dual band power amplifier have used modify stub matching for single FET, center frequency 2.14GHz and 5.2GHz respectively. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of the all harmonic components is very difficult m dual-band, we have managed only the second- and third-harmonics to obtain the high efficiency with the CRLH TL in dual-band. Dual-band characteristics in the output has to balance. Two operating frequencies are chosen at 2.14 GHz and 5.2 GHz in this work. The measured results show that the output power of 28.56 dBm and 29 dBm was obtained at 2.14 GHz and 5.2 GHz, respectively. At this point, we have obtained the power-added efficiency (PAE) of 65.824 % and 69.86 % at two operation frequencies, respectively.