• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.194-197
• /
• 2002

Applying dual layer insulator on plastic substrates improved electrical characteristics of organic thin film transistor(TFT). A high-quality silicon dioxide(SiO$_2$) suitable for a insulator was deposited on plastic substrates by e-beam evaporation at 110$^{\circ}C$. The insulator film which was treated by N$_2$ annealing at 150$^{\circ}C$ showed excellent I-V, C-V characteristics. The dual layer insulator structure of polyimide-SiO$_2$ improved the roughness of SiO$_2$ surface and showed very low leakage current. In addition, the flat band voltage has been reduced from -2.5V to about 0.5V.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.8
• /
• pp.53-61
• /
• 1994

Intermetallic dielectric layer was formed by using SiO$_2$/SOG/SiO$_2$ for aluminum based dual-metal interconnection process and its electric characteristics were evaluated. The dielectric layer was in the cost and facility point of view more useful than the insulator that was formed by etch-back process. The planarity by using SOG process was about 40% higher than that of the insulator by the CVD process. When SiO$_2$ films were deposited by the PECVD process the Al hillock formation during the next process was restrained bucause the intermetalic insulator was made at low temperature. The leakage current was 1${\times}10^{7}~1{\times}10^{-8}A/cm^{2}$ at the electric field of 10$^{5}$V/cm and breakdown filed was 4.5${\times}10^{6}~7{\times}10^{6}A/cm$. So we had confirmed that siloxane SOG was very useful for intermetallic layer material.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2015.08a
• /
• pp.215.2-215.2
• /
• 2015

We fabricated dual active layer (DAL) thin film transistors (TFTs) with indium tin zinc oxide (ITZO) and indium gallium zinc oxide (IGZO) thin film layers using solution process. The ITZO and IGZO layer were used as the front and back channel, respectively. In order to investigate the bias stress stability of ITZO SAL (single active layer) and ITZO/IGZO DAL TFT, a gate bias stress of 10 V was applied for 1500 s under the dark condition. The SAL TFT composed of ITZO layer shows a poor positive bias stability of ${\delta}VTH$ of 13.7 V, whereas ${\delta}VTH$ of ITZO/IGZO DAL TFT was very small as 2.6 V. In order to find out the evidence of improved bias stress stability, we calculated the total trap density NT near the channel/gate insulator interface. The calculated NT of DAL and SAL TFT were $4.59{\times}10^{11}$ and $2.03{\times}10^{11}cm^{-2}$, respectively. The reason for improved bias stress stability is due to the reduction of defect sites such as pin-hole and pores in the active layer.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.5
• /
• pp.318-323
• /
• 2015

We present a new way to create a thermally stable, highly strained germanium (Ge) optical resonator using a novel Ge-on-dual-insulators substrate. Instead of using a conventional way to undercut the oxide layer of a Ge-on-single-insulator substrate for inducing tensile strain in germanium, we use thin aluminum oxide as a sacrificial layer. By eliminating the air gap underneath the active germanium layer, we achieve an optically insulating, thermally conductive, and highly strained Ge resonator structure that is critical for a practical germanium laser. Using Raman spectroscopy and photoluminescence experiments, we prove that the novel geometry of our Ge resonator structure provides a significant improvement in thermal stability while maintaining good optical confinement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.288-291
• /
• 2004

Due to the charge compensation effect, SOI(Silicon-On-Insulator) LIGBT with dual-epi layer have been found to exhibit both low forward voltage drop and high static breakdown voltage. In this paper, electrical characteristics of the SOI LIGBT with dual-epi structure is presented. Trenched anode structure is employed to obtain uniform current flowlines and shorted anode structure also employed to prevent the fast latch-up. Latching current density of the proposed LIGBT with $T_1=T_2=2.5{\mu}m,\;N_1=7{\times}10^{15}/cm^3,\;N_2=3{\times}10^{15}/cm^3$ is $800A/cm^2$ and breakdown voltage is 125V while latching current density and breakdown voltage of the conventional LIGBT is $700A/cm^2$ and 55V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.110-111
• /
• 2006

이중 에피층을 가지는 SOI (Silicon-On-Insulator) RESURF(REduced SURface Field) LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자의 에피층 두께에 따른 항복전압 특성을 분석하였다. 이중 에 피층 구조를 가지는 SOI RESURF LIGBT 소자는 전하보상효과를 얻기 위해 기존 LIGBT 소자의 n 에피로 된 영역을 n/p 에피층의 이중 구조로 변경한 소자로 n/p 에피층 영역내의 전하간 상호작용에 의해 에피 영역 전체가 공핍됨으로써 높은 에피 영역농도에서도 높은 항복전압을 얻을 수 있는 소자이다. 본 논문에서는 LIGBT 에피층의 전체 두께와 농도를 고정한 상태에서 n/p 에피층의 두께가 변하는 경우에 항복전압 특성의 변화에 대해 simulation을 통해 분석하였다.

• Proceedings of the KIEE Conference
• /
• 2004.07c
• /
• pp.1585-1587
• /
• 2004

이중 에피층 구조를 가지는 SOI(Silicon-On-Insulator) LIGBT(Lateral Insulated Gate Bipolar Transistor)의 에피층 두께 변화에 따른 항복전압 특성을 분석하였다. 제안된 소자는 전하보상효과를 얻기 위해 n/p-epi의 이중 에피층 구조를 사용하였으며, 에피층 전체에 걸쳐서 전류가 흐를 수 있도록 하기 위해 trenched anode구조를 채택하였다. 본 논문에서는 n/p-epi층의 농도를 고정시킨 후 각각의 epi층의 두께를 변화시켜가며 simulation을 수행하였을 때 항복전압의 변화 및 표면과 epi층에서의 전계분포변화를 분석하였다.