• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.125-135
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• 2009

An analytical 2-dimensional model to explain the small signal and noise properties of an AlGaN/GaN modulation doped field effect transistor has been developed. The model is based on the solution of two-dimensional Poisson's equation. The developed model explains the influence of Noise in ohmic region (Johnson noise or Thermal noise) as well as in saturated region (spontaneous generation of dipole layers in the saturated region). Small signal parameters are obtained and are used to calculate the different noise parameters. All the results have been compared with the experimental data and show an excellent agreement and the validity of our model.

• 한국결정성장학회지
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• 제12권3호
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• pp.161-164
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• 2002

Polycrystalline and epitaxial heterostructure films of $La_{0.5}Sr_{0.5}CoO_{3}/Pb(Nb_{0.04}Zr_{0.28}Ti_{0.68})O_{3}/La_{0.5}Sr_{0.5}CoO_{3}$ (LSCO/PNZT/LSCO) capacitors were evaluated in terms of low voltage and high speed operation in high density memory, using TiN/Pt conducting barrier combination. Structural studies for a high density ferroelectric memory process flow, which requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack, indicate complete phase purity (i.e. fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, and high-speed characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.

• 한국지반환경공학회 논문집
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• 제17권2호
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• pp.31-39
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• 2016

일반적으로 고함수비를 가진 연약지반의 경우 압밀 촉진을 원활히 하기 위하여 연직배수재를 주로 사용하고 있다. 부산 점토는 대심도 연약지반 아래에 존재하는 모래 및 자갈 대수층에 피압이 관측되었다. 그러나 연직배수재가 설치된 연약지반에 피압이 미치는 영향에 대한 조사나 연구는 미미한 실정이다. 따라서 본 논문에서는 연직배수재가 설치된 부산 낙동강 하구 연약지반에 피압의 작용 유 무에 따른 압밀 거동을 조사하기 위해 일차원 대형 컬럼 장치를 제작하여 점토지반의 압밀 거동 실험을 수행하였다. 실험 결과 최종 침하량은 피압이 작용하는 지반이 피압이 작용하지 않는 지반보다 더 크게 나타났다. 이는 피압의 상향침투로 인해 점토층의 유효응력이 감소하여 나타난 결과로 판단된다. 또한 피압이 작용하는 지반의 경우 과잉간극수압이 완전 소산되지 않고 잔류하는 것으로 나타났으며, 비배수 전단강도는 피압이 작용하지 않는 지반에 비해 상대적으로 낮은 값을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• 펄프종이기술
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• 제33권4호
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• pp.21-27
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• 2001

Korean traditional paper (Hanji) making technology has adopted two kinds of sheet forming processes, which called "Oebal-choji": and "Ssangbal-choji". The sheet forming process of Oebal-choji is an original method developed in Korea. At first, paper stock is dipped onto the mold and flow away in the forward direction. Then, paper stock is scooped again and rhythmically rocked from side to side, this work is repeated several times. Through this operation the fibers intertwine and paper layers are formed. Ssangbal-choji is almost same as the Nagashizuki, which used in Japan. In this method, paper stock is scooped onto the mold and rhythmically rocked backwards and forwards several times, the water drains slowly through the bamboo screen and then sheet is formed. Tamezuki method is used in Japan and China. This is a method in which the mold is dipped into the paper stock once and left to drain. In the Ssangbal-choji and Nagashizuki methods, the most of excess solution is cast out while in the Tamezuki all of it is allowed to drain through the mold. This study was carried out to investigate the physical properties of the Hanjis that were made by Oebal-choji, Ssangbal-choji, Nagashizuki, and Tamezuki sheet forming processes. The results were follows; Physical properties of the Oebal-choji Hanji were better than those of Ssangbal-choji, Nagashizuki, and Tamezuki. Oebal-choji Hanji made little difference of paper strength between MD and CD, but Ssangbal-chjo and Nagashizuki Hanjis made wide difference. And there are no difference of paper strength between MD and CD on the Tamezuki Hanji. On the confocal laser scanning microscopy (CLSM) observation of the Hanjis, Oebal-choji made well crossed fiber orientation than those of other forming processes.r forming processes.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Transactions on Electrical and Electronic Materials
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• 제1권4호
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• pp.1-6
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• 2000

The mechanical strength of silicon carbide dose nor permit the use of diffusion as a means to achieve selective doping as required by most electronic devices. While epitaxial layers may be doped during growth, ion implantation is needed to define such regions as drain and source wells, junction isolation regions, and so on. Ion activation without an annealing cap results in serious crystal damage as these activation processes must be carried out at temperatures on the order of 1600$^{\circ}C$. Ion implanted silicon carbide that is annealed in either a vacuum or argon environment usually results in a surface morphology that is highly irregular due to the out diffusion of Si atoms. We have developed and report a successful process of using silicon overpressure, provided by silane in a CAD reactor during the anneal, to prevent the destruction of the silicon carbide surface, This process has proved to be robust and has resulted in ion activation at a annealing temperature of 1600$^{\circ}C$ without degradation of the crystal surface as determined by AFM and RBS. In addition XPS was used to look at the surface and near surface chemical states for annealing temperatures of up to 1700$^{\circ}C$. The surface and near surface regions to approximately 6 nm in depth was observed to contain no free silicon or other impurities thus indicating that the process developed results in an atomically clean SiC surface and near surface region within the detection limits of the instrument(${\pm}$1 at %).

• 한국전기전자재료학회논문지
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• 제22권11호
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• pp.910-917
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• 2009

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1174-1177
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• 2006

A bottom contact organic thin film transistor (OTFT) is fabricated with an organic double-layered gate insulator (GI) and pentacene. The PMMA and MNB layers are treated on gate insulator and source/drain (S/D, Au) before depositing pentacene to investigate device properties and pentacene growth. The sequence of surface treatment affects a device performance seriously. The ultra-thin PMMA (below 50A) was deposited on organic gate insulator and S/D metal by spin coating method, which showed no deterioration of on-state current (Ion) although bottom contact structure was exploited. We proposed that the reason of no contact resistance (Rc) increase may be due to a wettability difference in between PMMA / Au and PMMA / organic GI. As a result, the device treated by $PMMA\;{\rightarrow}\;MNB$ showed much better Ion behavior than those fabricated by $MNB\;{\rightarrow}\;PMMA$. We will report the important physical and electrical performance difference associated with surface treatment sequence.