• 제목/요약/키워드: Drain engineering

검색결과 987건 처리시간 0.031초

PBD의 유효등가경 평가에 관한 연구 (Study on Estimation of Equivalent Circle of Plastic Board Drain)

  • 유승경;이충호;윤길림;김병탁
    • 한국지반공학회:학술대회논문집
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    • 한국지반공학회 2006년도 추계 학술발표회
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    • pp.490-496
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    • 2006
  • In order to design accurately plastic board drain (PBB) method, it is important to determine the equivalent circle of PBD. In this paper, a series of numerical analyses on soft ground improved by PBD were carried out, in order to investigate the resonable equivalent circle of PBD considering consolidation behavior of improved soft ground by PBD. The applicability of numerical analyses, in which an elasto-viscoplastic three-dimensional consolidation finite element method was applied, could be confirmed comparing with results of a series of model tests on consolidation behaviors of soft ground improved by PBD. And, through the results of the numerical analyses, consolidation behaviors of soft ground during consolidation was elucidated, together with the equivalent circle of PBD considering consolidation behaviors.

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Drain-current Modeling of Sub-70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions

  • Lim, In Eui;Jhon, Heesauk;Yoon, Gyuhan;Choi, Woo Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권1호
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    • pp.94-100
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    • 2017
  • Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

Gate-to-Drain Capacitance Dependent Model for Noise Performance Evaluation of InAlAs/InGaAs Double-gate HEMT

  • Bhattacharya, Monika;Jogi, Jyotika;Gupta, R.S.;Gupta, Mridula
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권4호
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    • pp.331-341
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    • 2013
  • In the present work, the effect of the gate-to-drain capacitance ($C_{gd}$) on the noise performance of a symmetric tied-gate $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters ($Y_{11}$ and $Y_{21}$ which are obtained incorporating the effect of $C_{gd}$), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.

An Experimental Study on Reducing Condensation in Marine Air Compressors

  • Kim, Bu-Gi;Kim, Hong-Ryeol;Yang, Chang-Jo;Kim, Jun-Ho
    • 해양환경안전학회지
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    • 제21권3호
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    • pp.303-308
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    • 2015
  • Compressed air has many uses on board ship, ranging from diesel engine starting to the cleaning of machinery during maintenance. In an effort to enhance the performance of the marine compressed air system, this work studied a way to reduce condensation from the air compressor via experiments. Especially more condensation is produced when the temperature at compressor outlets and the humidity of the air are higher. so in the research, drain production change has been observed by additionally installing the cooling fan on the suction portion of the air to air compressor and this is the method for reducing the compressed air drain that has passed through the compressor. For the result, it was verified that when the cooling fan was used, less drain was made where per hour it was 500.9ml of drain and the measured result after installing the cooling fan was that less drain was made. Other additional and various researches are needed including experiments like silica gel passing through the suction portion afterwards.

포항 점토 지반의 수평배수 압밀특성 연구 (A Study on Character of Consolidation for Radial Drainage of Pohang배s Clay Ground)

  • 이송;전제성;김원영
    • 한국지반공학회:학술대회논문집
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    • 한국지반공학회 2000년도 봄 학술발표회 논문집
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    • pp.685-692
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    • 2000
  • Vertical drain used improvement soft clay is made of not only decreasing construction time but also increasing the ground strength during some decades. As, it is applied to improvement soft clay with vertical drain, it is designed by the result that is caused by oedemeter test ignored anisotropic of the ground related to consolidation conditions. When we are expected consolidation conditions, the most important factors is soil of compaction and water permeability. Above all, anisotropic of the ground permeability show the results which differ between vertical and radial drainage. Recently, We study for radial consolidation coefficient and permeability coefficient that utilized Rowe Cell Consolidation and permeability tester but, it dont use well because of not only a supply lack also difficulty of test. The paper experimented with searching anisotropic of the ground so there are Rowe Cell test, standard consolidation tester and modified standard consolidation test that have pohang's soft clay ground. Therefore, we find anisotropic of the ground and a tester of easy use more than before. We made a comparison test result between the devised tester and Rowe Cell tester, Also, we learned average degree of consolidation for partial penetrating vertical drains. We were found relations as effective stress-void and effective stress-permeability coefficient through those tests.

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복합통수능시험기를 이용한 실린더형 플라스틱 보드 드레인의 성능 평가 (Capacity Evaluation of Cylindrical Plastic Board Drain with The Composite Discharge Capacity Apparatus)

  • 이찬우;정두회;김윤태;진규남
    • 한국지반공학회:학술대회논문집
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    • 한국지반공학회 2008년도 춘계 학술발표회 초청강연 및 논문집
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    • pp.293-299
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    • 2008
  • If a conventional type of Plastic Board Drain (PBD) is installed to the deep clay deposit, it is subjected to a high lateral earth pressure. a flow channel of PBD may be reduced by the collapse of cores and clogged by the intrusion of filter into the space between cores which are made by lateral pressure. It could decrease the ability of initial discharge capacity and the reliability of long term discharge capacity. A cylindrical plastic board drain (C-PBD) considered in this study consists of cylindrical core and several supports so that it can prevent the reduction of area of flow channel from the higher lateral earth pressure effectively. The discharge capacity of C-PBD was compared to that of a conventional PBD through performing experiments using the composite discharge capacity apparatus which can consider in-situ condition such as penetration of drains, ground settlement and discharge capacity. As a result, C-PBD showed much better performance than PBD in the ability of discharge. It was observed that the C-PBD was folded whereas the conventional PBD was folded after the experiment.

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드레인 전압 종속 게이트-벌크 MOSFET 캐패시턴스 추출 데이터를 사용한 측면 채널 도핑 분포 측정 (Lateral Channel Doping Profile Measurements Using Extraction Data of Drain Voltage-Dependent Gate-Bulk MOSFET Capacitance)

  • 최민권;김주영;이성현
    • 대한전자공학회논문지SD
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    • 제48권10호
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    • pp.62-66
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    • 2011
  • 본 연구에서는 측정된 S-파라미터를 사용하여 드레인-소스 전압 Vds에 무관한 게이트-소스 overlap 캐패시턴스를 추출하고, 이를 바탕으로 deep-submicron MOSFET의 Vds 종속 게이트-벌크 캐패시턴스 곡선을 추출하는 RF 방법이 새롭게 개발 되었다. 추출된 캐패시턴스 값들을 사용한 등가회로 모델과 측정된 데이터가 잘 일치하는 것을 관찰함으로써 추출방법의 정확도가 검증되었다. 추출된 데이터로부터 overlap과 depletion 길이의 Vds 종속 곡선이 얻어졌으며, 이를 통해 drain 영역의 채널 도핑 분포를 실험적으로 측정하였다.

Experimental Investigation of Physical Mechanism for Asymmetrical Degradation in Amorphous InGaZnO Thin-film Transistors under Simultaneous Gate and Drain Bias Stresses

  • Jeong, Chan-Yong;Kim, Hee-Joong;Lee, Jeong-Hwan;Kwon, Hyuck-In
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권2호
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    • pp.239-244
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    • 2017
  • We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source ($V_{GS}$) and drain-to-source ($V_{DS}$) bias stresses of ($V_{GS}=24V$, $V_{DS}=15.9V$) and ($V_{GS}=22V$, $V_{DS}=20V$), but the asymmetrical degradation is more significant after the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress ($V_{GS}$, $V_{DS}$) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance ($R_S$) and the voltage drop at $R_S$ ($V_{S,\;drop}$) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and $V_{S,\;drop}$ are extracted under the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.

실리콘 선택적 결정 성장 공정을 이용한 Elevated Source/drain물 갖는 NMOSFETs 소자의 특성 연구 (A Study on the Device Characteristics of NMOSFETs Having Elevated Source/drain Made by Selective Epitaxial Growth(SEG) of Silicon)

  • 김영신;이기암;박정호
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제51권3호
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    • pp.134-140
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    • 2002
  • Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.