• JSTS:Journal of Semiconductor Technology and Science
• /
• 제10권4호
• /
• pp.265-275
• /
• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제11권3호
• /
• pp.169-181
• /
• 2011

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: $g_{m1}$, $g_{m2}$, $g_{m3}$, and figure-of-merit (FOM) metrics; $V_{IP2}$, $V_{IP3}$, IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth ($X_j$) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

• Transactions on Electrical and Electronic Materials
• /
• 제17권6호
• /
• pp.329-334
• /
• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• 한국전기전자재료학회논문지
• /
• 제23권10호
• /
• pp.763-766
• /
• 2010

By improving the conducting process of metal source/drain (S/D) in direct contact with the channel, schottky barrier metal-oxide-semiconductor field effect transistors (SB MOSFETs) reveal low extrinsic parasitic resistances, offer easy processing and allow for well-defined device geometries down to the smallest dimensions. In this work, we investigated the arrhenius plots of the SB MOSFETs with different S/D schottky barrier (SB) heights between simulated and experimental current-voltage characteristics. We fabricated SB MOSFETs using difference S/D metals such as Cr (${\Phi}_{Cr}$ ~4.5 eV) and Ni (${\Phi}_{Ni}$~5.2 eV), respectively. Schottky barrier height (${\Phi}_B$) of the fabricated devices were measured to be 0.25~0.31 eV (Cr-S/D device) and 0.16~0.18 eV (Ni-S/D device), respectively in the temperature range of 300 K and 475 K. The experimental results have been compared with 2-dimensional simulations, which allowed bandgap diagram analysis.

• 한국군사과학기술학회지
• /
• 제12권4호
• /
• pp.483-490
• /
• 2009

In this paper, a novel low-damage silicon nitride passivation for 100nm InAlAs/InGaAs MHEMTs has been developed using remote ICPCVD. The silicon nitride deposited by ICPCVD showed higher quality, higher density, and lower hydrogen concentration than those of silicon nitride deposited by PECVD. In particular, we successfully minimized the plasma damage by separating the silicon nitride deposition region remotely from ICP generation region, typically with distance of 34cm. The silicon nitride passivation with remote ICPCVD has been successfully demonstrated on GaAs MHEMTs with minimized damage. The passivated devices showed considerable improvement in DC characteristics and also exhibited excellent RF characteristics($f_T$of 200GHz).The devices with remote ICPCVD passivation of 50nm silicon nitride exhibited 22% improvement(535mS/mm to 654mS/mm) of a maximum extrinsic transconductance($g_{m.max}$) and 20% improvement(551mA/mm to 662mA/mm) of a maximum saturation drain current ($I_{DS.max}$) compared to those of unpassivated ones, respectively. The results achieved in this work demonstrate that remote ICPCVD is a suitable candidate for the next-generation MHEMT passivation technique.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2012년도 춘계학술발표대회
• /
• pp.67.1-67.1
• /
• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2013년도 춘계학술대회 논문집
• /
• pp.154-154
• /
• 2013

In this work, we investigated the characteristics and the effects of light on the negative gate bias stress stability (NBS) in high mobility polycrystalline IGO TFTs. IGO TFT showed a high drain current on/off ratio of ${\sim}10^9$, a field-effect mobility of $114cm^2/Vs$, a threshold voltage of -4V, and a subthresholdslpe(SS) of 0.28V/decade from log($I_{DS}$) vs $V_{GS}$. IGO TFTs showed large negative $V_{TH}$ shift(17V) at light power of $5mW/cm^2$ with negative gate bias stress of -10V for 10000seconds, at a fixed drain voltage ($V_{DS}$) of 0.5V.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권1호
• /
• pp.43-47
• /
• 2013

In this work, we report extraction of the density-of-states (DOS) in polymer-based organic thin film transistors through the multi-frequency C-V spectroscopy. Extracted DOS is implemented into a TCAD simulator and obtained a consistent output curves with non-linear characteristics considering the contact resistance effect. We employed a Schottky contact model for the source and drain to fully reproduce a strong nonlinearity with proper physical mechanisms in the output characteristics even under a very small drain biases. For experimental verification of the model and extracted DOS, 2 different OTFTs (P3HT and PQT-12) are employed. By controlling the Schottky contact model parameters in the TCAD simulator, we accurately reproduced the nonlinearity in the output characteristics of OTFT.

• 한국지반공학회:학술대회논문집
• /
• 한국지반공학회 2009년도 세계 도시지반공학 심포지엄
• /
• pp.449-456
• /
• 2009

As soft grounds have complex engineering properties that the load bearing capacity is low and high compressibility, it needs to solve this problems prior to structures are constructed by the method of improvement of soft ground. Generally, the sand mat is used to as a horizontal drain material and loading base for soft ground improvement work. However, as the natural environment can be damaged by sand pickings of large quantity and the volume which is enormous and an amount of demanded sand is increased, it is state of short in supply. This paper presents the result of field experimental test to use Precious Slag Ball to solve these issues instead of sand mat as the replacing material. This study evaluated the performance of Precious Slag Ball as a sand mat in terms of discharge capacity, settlement, and settlement through the K-Embank program.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
• /
• pp.1600-1603
• /
• 2009

In this work, we have fabricated inverted staggered ZnO TFTs with 1-${\mu}m$ resolution channel length by micro contact printing (${\mu}$-CP) method. Patterning of micro scale source/drain electrodes without etching is successfully achieved by micro contact printing method by using silver ink and polydimethylsiloxane (PDMS) stamp. And the time dependent characteristics of the sheet resistance show that Ag inklayer could be used as source and drain electrodes for ZnO TFTs.