• Korean Management Science Review
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• v.11 no.3
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• pp.47-54
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• 1994

본 연구에서는 선형계획법 프로그램을 실무용과 교육용 모두 사용할 수 있는 사용자 편의성이 강조된 선형계획법 통합환경 프로그램인 LIPED를 개발하였다. LIPED는 첫째, 풀다운(Pull Down) 메뉴 방식의 선형계획법 통합환경, 둘째, 선형계획법의 교육을 위해 여러가지 선형계획법해법 들을 통합하여 구축하였다. 셋째, 실무용으로 사용할 수 있는 안정적이고 효율적인 선형계획법 프로그램을 제공한다. 마지막으로 실험용 선형계획법 문제를 생성할 수 있는 기능과 다양한 선형계획법 입력 방식과 각 방식이 호환되도록 구축하였다. 그리고 추후연구로 교육용 LP에 Affine Scaling Algorithm, Barrier Algorithm을 추가하고, UNIX System 또는 Windows 환경하에서 통합 프로그램의 개발 및 수식 형태의 입력방식과 스프레드쉬트(Spreadsheet) 형식의 입력방식 등의 다양한 입력방식의 지원과 전문가의 지식을 연결하여 해법 선택 및 모형 구축 등을 지원할 수 있는 지능형 선형계획법 지원시스템을 구축하고 있다.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1130-1137
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• 2009

This paper describes a scaled model development of PMSG wind power system using wind turbine simulator and matrix converter. The wind turbine simulator, which consists of an induction motor with vector drive, calculates the output torque of a specific wind turbine using simulation software and sends the torque signal to the vector drive after scaling down the calculated value. The operational feasibility of interconnected PMSG system with matrix converter was verified by computer simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was conformed by experimental works with a laboratory scaled-model of wind power system. The simulation and experimental results confirm that matrix converter can be effectively applied for the PMSG wind power system.

• Explosives and Blasting
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• v.16 no.3
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• pp.25-34
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• 1998

This area is covered in Andesite of high compression strength and located in PUSAN SEO-KU. There are many old houses around shaft site. So, we must have a cautious blasting operation. A total of 40 blasts were test at DAE-SHIN Shaft site to study the magnitude and frequency characterization of blast-induced vibration. The effect of viblating frequency on structual damage and site-specific scaling to define th empirical equations were also discussed. The result can be summarized as follows: 1. Some empirical equations were obtained. $V=K\{{\frac{D}{W}}1/3\}^{-n}$ where the values for n and K are estimated to be -1.407 to -2.202 and 643.3489 to 7283.2104 respectively. 2. Dominant frequencies at short distance are in the range of about 75.0 to 91.8 Hz, with some exceptions of about 50Hz, Frequencies observed at long distance are in the range of 10 to 2Hz. It is apparent the shift of dominant frequency down to lower levels at long distance.

• Journal of the Korean Society of Propulsion Engineers
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• v.8 no.2
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• pp.54-61
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• 2004

Miniaturization of subsystems including propulsion systems is recent trends in spacecraft technology. Small space vehicle propulsion is not only a technological challenge of a scaling system down, but also a combination of fundamental flow/combustion constraints. In this paper, physical constraints of micronozzle for cold gas micro-thruster are reviewed and discussed. Method to measure small thrust are also described.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.1-10
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• 2007

In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.

• Electrical & Electronic Materials
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• v.7 no.2
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• pp.123-129
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• 1994

SONOS EEPROM chips, containing several SONOSFET nonvolatile memories of various channel size, have been fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM ($1.2\mu\textrm{m}$.m design rule). All the SONOSFET memories have the triple insulated-gate consisting of 30.angs. tunneling oxide, 205.angs. nitride and 65.angs. blocking oxide. The miniaturization of the devices for the higher density EEPROM and their characteristics alterations accompanied with the scaling-down have been investigated. The stabler operating characteristics were attained by increasing the ratio of the channel width to length. Also, the transfer, switching, retention and degradation characteristics of the most favorable performance devices were presented and discussed.

• Electrical & Electronic Materials
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• v.7 no.2
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• pp.107-116
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• 1994

In the manufacturing of VLSI circuits, variations of device characteristics due to the slight differences in process parameters drastically aggravate the performances of fabricated devices. Therefore, it is very important to establish optimal process conditions in order to minimize deviations of device characteristics. In this paper, we used one-dimensional process simulator, SUPREM-II, and two dimensional device simulator, MINIMOS 4.0 in order to extract optimal process parameter which can minimize changes of the device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derived the dependence relations between process parameters and device characteristics. Here, we have suggested a method to extract process parameters from design trend curve(DTC) obtained by these dependence relations. And we have discussed short channel effects and device limitations by scaling down MOSFET dimensions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.51-58
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• 1995

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si cosumption phenomenon during silicidation. We can solve these problems by As preamorphization of the predeposited amorphous Si layer. The predeposited amorphous Si layer made the junction depth decrease to nearly the thickness value of the layer and was effectively utilized as the cosumed Si source during Ti silicidation. This method was applied to the actual fabrication of PMOSFET through SES (selectricely etched Si) techology.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.48.1-48.1
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• 2010

Cu has been used for metallic interconnects in ULSI applications because of its lower resistivity according to the scaling down of semiconductor devices. The resistivity of Cu lines will affect the RC delay and will limit signal propagation in integrated circuits. In this study, we investigated the characteristics of electroplated Cu films according to the variation of concentration of organic additives. The plating electrolyte composed of $CuSO_4{\cdot}5H_2O$, $H_2SO_4$ and HCl, was fixed. The sheet resistance was measured with a four-point probe and the material properties were investigated with XRD (X-ray Diffraction), AFM (Atomic Force Microscope), FE-SEM (Field Emission Scanning Electron Microscope) and XPS (X-ray Photoelectron Spectroscopy). From these experimental results, we found that the organic additives play an important role in formation of Cu film with lower resistivity by EPD.