• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.296-299
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• 2013

디스플레이 기술이 발전함에 따라 다양한 크기의 디스플레이를 탑재한 장치들이 등장하게 되었고, 다양한 디스플레이 크기만큼 다양한 해상도를 사용하고 있다. 때문에 비디오 코덱과 scaler는 보편적으로 함께 사용된다. 그러나 기존의 scaler는 비디오 코덱의 복호화기와 화면 해상도 변환 모듈이 독립적으로 구성되고, 서로 간에 정보를 이용하지 않으므로 시스템의 성능 개선에 한계가 존재하였다. 즉, 비디오 코덱의 복호화기는 비트스트림으로부터 복호한 정보를 바탕으로 영상을 복원하고, 복원영상은 up/down scaler에서 확대/축소를 수행한다. 하지만 비디오 코덱의 비트스트림에 존재하는 정보는 영상의 특성을 반영하기 때문에 up/down scaler에서 비디오 코덱의 복호화기에서 복호된 정보를 이용하면 복잡도의 증가 없이 효율적인 확대/축소를 수행할 수 있다. 이에 본 논문에서는 비디오 코덱 중 차세대 비디오 코덱인 H.264/AVC 복호화기에서 생성된 복원 영상에 대해서 별도로 영상의 특성을 계산하는 모듈 없이 H.264/AVC 복호화기에서 복원된 정보 중 인트라 모드 정보를 바탕으로 영상의 특성에 맞는 up/down scaler를 구현하는 방법을 제안한다. 이 방법은 기존의 scaler들보다 물체의 경계영역을 더 선명하게 확대하는 효과를 보인다.

• Advances in nano research
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• v.14 no.1
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• pp.1-15
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• 2023

Driven by the scaling down of transistor node technology, graphene became of interest to many researchers following the success of its fabrication as graphene nanoribbons (GNRs). However, during the fabrication of GNRs, it is not uncommon to have defects within the GNR structures. Scaling down node technology also changes the modelling approach from the classical Boltzmann transport equation to the quantum transport theory because the quantum confinement effects become significant at sub-10 nanometer dimensions. The aim of this study is to examine the effect of Stone-Wales defects on the electronic properties of GNRs using a tight-binding model, based on Non-Equilibrium Green's Function (NEGF) via numeric computation methods using MATLAB. Armchair and zigzag edge defects are also implemented in the GNR structures to mimic the practical fabrication process. Electronic properties of pristine and defected GNRs of various lengths and widths were computed, including their band structure and density of states (DOS). The results show that Stone-Wales defects cause fluctuation in the band structure and increase the bandgap values for both armchair GNRs (AGNRs) and zigzag GNRs (ZGNRs) at every simulated width. In addition, Stone-Wales defects reduce the numerical computation DOS for both AGNRs and ZGNRs. However, when the lengths of the structures increase with fixed widths, the effect of the Stone-Wales defects become less significant.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.5
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• pp.842-849
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• 2011

The transponder simulator designed to simulate the transponder of military satellite communication systems in the geostationary orbit is required to have time delay function, because of 250 ms delay time, when a radio wave transmits the distance of 36,000 km in free space. But, it is very difficult to develop 250 ms time delay device in the transponder simulator of 100 MHz bandwidth, due to unstable operation of FPGA, loss of memory data for the high speed rate signal processing. Up to date, bandwidth of the time delay device is limited to 45 MHz bandwidth. To solve this problem, we propose the new time delay techniques up to 100 MHz bandwidth without data loss. Proposed techniques are the low speed down scaling and high speed up scaling methods to read and write the external memory, and the matrix structure design of FPGA memory to treat data as high speed rate. We developed the satellite link simulator in 100 MHz bandwidth using the proposed new time delay techniques, implemented to the transponder simulator and verified the function of 265 ms time delay device in 100 MHz bandwidth.

• Electrical & Electronic Materials
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• v.9 no.5
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• pp.476-482
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• 1996

The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.

• Nuclear Engineering and Technology
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• v.33 no.3
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• pp.315-326
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• 2001

Direct ECC bypass phenomena that occur in a reactor vessel downcomer with a Direct Vessel Injection (DVI) system during the reflood phase of a Large Break Loss-of-Coolant Accident (LBLOCA) are experimentally investigated using a transparent l/7.5 scaled down test facility of the Upper Plenum Test Facility (UPTF). A series of separate effect tests are peformed in order to investigate the mechanisms of direct ECC bypass and to find out its scaling parameters. Various flow regimes and phasic distribution in downcomer are identified and mapped, and the fraction of direct ECC bypass is measured under a wide range of air and water injection conditions. From the counterpart test of the UPTF Test 21-D, the dimensionless gas velocity ( $j^{*}$$_{g,eff}$) is derived experimentally, which is believed to be a major scaling parameter for the fraction of direct ECC bypass. And it is found out that the direct ECC bypass is greatly affected by the spreading width of ECC water film and the geometric configuration of the downcomer.r.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.317-320
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• 2001

In this paper, we have presented the simulation results about threshold voltage at Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n-channel MOSFETS with sate lengthes from 180 to 30 nm in accordance to constant voltage scaling theory. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region it due to scaling down. We investigated and analysed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Korea-Australia Rheology Journal
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• v.20 no.1
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• pp.27-34
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• 2008

Clay suspensions in liquid polymers exhibit a time-dependent behaviour that includes viscoelastic as well as thixotropic features. Because of the presence of interacting clay platelets, particulate networks can develop, which are broken down during flow and rebuild upon cessation of the flow. Here, the use of thixotropic techniques in probing flow-induced structures in nanocomposites is explored with data on a hectorite-poly(isobutylene) model system. By means of fast stress jump measurements the hydrodynamic contributions to the steady state stresses are determined as well as those caused by the stretching of the clay floes. Flow reversal measurements do not provide a clear indication of flow-induced anisotropy in the present case. The recovery of the clay microstructure upon cessation of flow is followed by means of overshoot and dynamic measurements. The development of a particulate network is detected by the appearance and growth of a low frequency plateau of the storage moduli. The modulus-frequency curves after various rest times collapse onto universal master curves, regardless of the pre-shear history or temperature. The scaling factors for this master curve are the crossover parameters. The crossover moduli are nearly a linear function of the crossover frequency, the relation being identical for recovery after shearing at different shear rates. This function depends, however, on temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Tunnel and Underground Space
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• v.12 no.2
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• pp.92-98
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• 2002

In this study reduced-scale experiments were conducted to analyze smoke movement in tunnel fire with jet fan, The 1/20 scale experiments were carried out under the froude scaling using gasoline pool fire range from 6.6 to 12.5 cm in diameter with total heat release rate from 0.714 to 4.77 kW. In the case of fires under the 2.5kW, backlaying was reduced about 40cm and smoke was effectively controled in downstream of the fan when operating the fan. The smoke layer was moved down and the ceiling temperature was decreased compared to that of without fan case in upstream of the fan, but the temperature in the lower part of the tunnel was increased.

• Journal of IKEEE
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• v.28 no.1
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• pp.26-32
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• 2024

Recently, various video resolution formats have emerged, and digital devices have built in dedicated scaler chips to support them by enlarging or reducing the resolution of input videos. Therefore, the performance and hardware size of scaler chips are important. In this paper, the combinatorial interpolation scaler algorithm proposed by Han is used to design the hardware using the line memory structure with dual-clock proposed by Han and Jung. The proposed hardware is capable of real-time processing in QHD environments, designed using Verilog, and validated using Xilinx's Vivado 2023.1. We also verify the performance of Han's proposed algorithm with a quantitative numerical evaluation of the proposed hardware.