• 제목/요약/키워드: Double-chip Technology

검색결과 73건 처리시간 0.019초

MOSFET의 부정합에 의한 출력옵셋 제거기능을 가진 윤곽검출용 시각칩의 설계 (Design of a Vision Chip for Edge Detection with an Elimination Function of Output Offset due to MOSFET Mismatch)

  • 박종호;김정환;이민호;신장규
    • 센서학회지
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    • 제11권5호
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    • pp.255-262
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    • 2002
  • 인간의 망막은 효율적으로 주어진 물체의 윤곽을 검출할 수 있다. 본 연구에서는 윤곽검출에 관여하는 망막 세포의 기능을 전자회로로 모델링하여 윤곽검출기능을 가지는 CMOS 시각칩을 설계하였다. CMOS 제조공정 중에는 여러 가지 요인에 의해 MOSFET의 특성이 변화할 수 있으며, 특히 어레이로 구성되어 각 픽셀의 신호를 출력하는 readout 회로에서의 특성변화는 출력옵셋으로 나타난다. 하드웨어로 입력영상의 윤곽을 검출하는 시각칩은 다른 응용시스템의 입력단에 사용되므로 이러한 옵셋은 전체 시스템의 성능을 결정하는 중요한 요소이다. 본 연구에서는 이와 같은 출력단의 옵셋을 제거하기 위해 CDS(Correlated Double Sampling) 회로를 이용한 윤곽 검출용 시각칩을 설계하였다. 설계된 시각칩은 CMOS 표준공정을 이용하여 다른 회로와 집적화가 가능하며, 기존의 시각칩보다 신뢰성 있는 출력특성을 나타냄으로써, 물체의 윤곽을 이용하는 물체추적, 지문인식, 인간 친화적 로봇시스템등의 다양한 응용 시스템의 입력단으로 적용될 수 있을 것이다.

단위 픽셀 회로의 간소화를 통해서 해상도를 향상시킨 이차원 윤곽 검출용 시각칩 (Vision chip for edge detection with resolution improvement through simplification of unit-pixel circuit)

  • 성동규;공재성;현효영;신장규
    • 센서학회지
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    • 제17권1호
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    • pp.15-22
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    • 2008
  • When designing image sensors including a CMOS vision chip for edge detection, resolution is a significant factor to evaluate the performance. It is hard to improve the resolution of a bio-inspired CMOS vision using a resistive network because the vision chip contains many circuits such as a resistive network and several signal processing circuits as well as photocircuits of general image sensors such as CMOS image sensor (CIS). Low resolution restricts the use of the application systems. In this paper, we improve the resolution through layout and circuit optimization. Furthermore, we have designed a printed circuit board using FPGA which controls the vision chip. The vision chip for edge detection has been designed and fabricated by using $0.35{\mu}m$ double-poly four-metal CMOS technology, and its output characteristics have been investigated.

미소전극어레이형 DNA칩을 이용한 유전자다형의 전기화학적 검출 (Electrochemical Detection of Single Nucleotide Polymorphism (SNP) Using Microelectrode Array on a DNA Chip)

  • 최용성;권영수;박대희
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제53권5호
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    • pp.286-292
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    • 2004
  • In this study, an integrated microelectrode array was fabricated on glass slide using microfabrication technology. Probe DNAs consisting of mercaptohexyl moiety at their 5-end were spotted on the gold electrode using micropipette or DNA arrayer utilizing the affinity between gold and sulfur. Cyclic voltammetry in 5mM ferricyanide/ferrocyanide solution at 100 ㎷/s confirmed the immobilization of probe DNA on the gold electrodes. When several DNAs were detected electrochemically, there was a difference between target DNA and control DNA in the anodic peak current values. It was derived from specific binding of Hoechst 33258 to the double stranded DNA due to hybridization of target DNA. It suggested that this DNA chip could recognize the sequence specific genes. It suggested that multichannel electrochemical DNA microarray is useful to develop a portable device for clinical gene diagnostic System.

Bump 회로를 이용한 Programmable CMOS Negative Resistor (A Programmable CMOS Negative Resistor using Bump Circuit)

  • 송한정
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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    • pp.253-256
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    • 2002
  • A programmable CMOS negative resistor has been designed and fabricated in a 0.5um double poly double metal technology. The proposed CMOS negative resistor consists of a positive feedback OTA and a bump circuit with Gaussian-like I-V curve. Measurements of the fabricated chip confirm that the proposed CMOS resistor shows various negative resistance according to control voltage.

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Integration of 5-V CMOS and High-Voltage Devices for Display Driver Applications

  • Kim, Jung-Dae;Park, Mun-Yang;Kang, Jin-Yeong;Lee, Sang-Yong;Koo, Jin-Gun;Nam, Kee-Soo
    • ETRI Journal
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    • 제20권1호
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    • pp.37-45
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    • 1998
  • Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

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Optimization of the Processing Parameters for Green Banana Chips and Packaging within Polyethylene Bags

  • Mitra, Pranabendu;Kim, Eun-Mi;Chang, Kyu-Seob
    • Food Science and Biotechnology
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    • 제16권6호
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    • pp.889-893
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    • 2007
  • The demand of quality green banana chips is increasing in the world snacks market, therefore, the preparation of quality chips and their subsequent shelf life in packaging were evaluated in this study. Banana slices were fried in hot oil to the desired moisture content (2-3%) and oil content (40%) in chips at 3 different temperatures, and the impact of different pretreatments were compared by sensory assessment. A linear relationship between time and temperature was used to achieve the optimal processing conditions. Banana slices fried at the lower temperature of $145^{\circ}C$ took longer to reach the desired chip qualities, but gave the best results in terms of color and texture. Blanching was the most effective pre-treatment for retaining the light yellow color in finished chips. For extending the shelf life of chips, moisture proof packaging in double layer high density polyethylene was more effective than single layer low density polyethylene.

CMOS Microcontroller IC와 고밀도 원형모양SOI 마이크로센서의 단일집적 (A Monolithic Integration with A High Density Circular-Shape SOI Microsensor and CMOS Microcontroller IC)

  • 이명옥;문양호
    • 전기전자학회논문지
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    • 제1권1호
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    • pp.1-10
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    • 1997
  • It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

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휨을 고려한 칩 패키지의 EMC/PCB 계면 접합 에너지 측정 (Measurement of EMC/PCB Interfacial Adhesion Energy of Chip Package Considering Warpage)

  • 김형준;안광호;오승진;김도한;김재성;김은숙;김택수
    • 마이크로전자및패키징학회지
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    • 제26권4호
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    • pp.101-105
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    • 2019
  • 칩 패키지에는 생산 공정 및 운송, 보관 과정에서 발생하는 외부 환경 변화로부터 인쇄 회로 기판(printed circuit board, PCB)을 보호하기 위해 에폭시 몰딩(epoxy molding compound, EMC)이 사용된다. PCB와 EMC의 접합 신뢰성은 제품의 품질 및 수명에 중요한 요소이며 이를 보증하기 위해 제품 설계 및 생산 단계에서 그 접합 에너지를 정밀하게 측정하고, 이에 영향을 끼치는 요소를 통제하여 공정을 최적화 시켜야 한다. 본 논문은 이중 외팔보(double cantilever beam, DCB) 시험을 이용하여 휨(warpage)이 있는 칩 패키지의 EMC와 PCB의 계면 접합 에너지를 측정하고 보정하는 방법에 대해 소개한다. DCB 시험법은 이종 재료의 계면 접합 에너지를 측정하는 전통적인 방법이며 정밀한 접합 에너지 측정을 위해 평평한 기판이 필수적이다. 그러나 칩 패키지는 내부 구성 요소들의 열팽창 계수 차이로 인해 휨이 발생하기 때문에 평평한 기판을 제작하여 정밀한 접합 에너지를 측정하는데 어려움이 있다. 이를 극복하고자 본 연구에서는 휨이 있는 칩 패키지로 DCB 시험법을 위한 시편을 제작하고, 기판의 복원력을 보정하여 접합 에너지를 계산하였다. 보정된 접합에너지는 동일 조건에서 제작된 칩 패키지 중 휨이 없는 시편을 선별하여 측정한 접합 에너지와 비교, 검증하였다.

A Ghost-Imaging System Based on a Microfluidic Chip

  • Wang, Kaimin;Han, Xiaoxuan;Ye, Hualong;Wang, Zhaorui;Zhang, Leihong;Hu, Jiafeng;Xu, Meiyong;Xin, Xiangjun;Zhang, Dawei
    • Current Optics and Photonics
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    • 제5권2호
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    • pp.147-154
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    • 2021
  • Microfluidic chip technology is a research focus in biology, chemistry, and medicine, for example. However, microfluidic chips are rarely applied in imaging, especially in ghost imaging. Thus in this work we propose a ghost-imaging system, in which we deploy a novel microfluidic chip modulator (MCM) constructed of double-layer zigzag micro pipelines. While in traditional situations a spatial light modulator (SLM) and supporting computers are required, we can get rid of active modulation devices and computers with this proposed scheme. The corresponding simulation analysis verifies good feasibility of the scheme, which can ensure the quality of data transmission and achieve convenient, fast ghost imaging passively.

Grinding Mechanism and Case Study on Double-Disc Grinding of Ferrous Sintered Material

  • Tanaka, Masaru;Yoshimoto, Akinori;Ohshita, Hideo;Hashimoto, Toshihiko
    • 한국분말야금학회:학술대회논문집
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    • 한국분말야금학회 2006년도 Extended Abstracts of 2006 POWDER METALLURGY World Congress Part2
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    • pp.877-878
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    • 2006
  • The sintered parts are mainly used for automobile industry, and a part of air conditioners. In automobile industry, the application range of sintered parts is very broad and use for a driving and a lubricating system. And air conditioner uses them for compressor. Grinding of compressor and pump parts is very difficult these days, because these parts use High hardness materials and require high precision grinding. Tool life has to be extended to decrease production cost. We analyzed processing mechanism and developed new grinding wheels for Double Disk Grinding. And, we introduce new truing technology that improved tool-life and precision.

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