• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.235-238
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• 1996

An inverted double channel AIGaAs/lnGaAs/GaAs heterostructure grown by LP-MOCVD is demonstrated and discussed. Sheet carrier densities in excess of $4.5{\times}10^{12}cm^{-2}$ at 300K are obtained with a hall mobility of $5010cm^2/V{\cdot}s$. The proposed device with a $1.8{\times}200{\mu}m^2$ gate dimension reveals an extrinsic transconductance as high as 320 mS/mm and a saturation current density as high as 820 mA/mm at 300K. This is the highest current density ever reported for GaAs MODFET's with the same gate length. Significantly improvements on gate voltage swing (up to 3.5 V) and on reverse breakdown voltage (-10V) are demonstrated due to inverted structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1840-1844
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• 2008

In this paper, the influence of channel doping concentration, which the most important factor is as double gate MOSFET is fabricated, on transport characteristics has been analyzed in the subthreshold region. The analytical model is used to derive transport model based on Poisson equation. The thermionic omission and tunneling current to have an influence on subthreshold current conduction are analyzed, and the relationship of doping concentration and subthreshold swings of this paper are compared with those of Medici two dimensional simulation, to verify this model. As a result, transport model presented in this paper is good agreement with two dimensional simulation model, and the transport characteristics have been considered according to the dimensional parameters of double gate MOSFET.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.50-55
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• 2022

Due to the wavelength shift problem of micro LED caused by the change of current density, the active matrix driving pixel circuit that is used in OLED cannot be applied to micro LED displays. Therefore, we need a gray scale method based on modulation of duration time of light emission. In this study, we propose the PWM-controlled micro LED pixel circuit based on CMOS thin film transistors (TFTs). By adopting CMOS inverter structure, we can reduce the number of storage capacitors from the circuit and make the operating speed of the circuit faster. Most of all, our circuit is designed to make operating speed of PWM circuit faster by adopting feedback effect through double gate TFT structure. As a result, it takes about 4.7ns to turn on the LED and about 5.6ns to turn it off. This operating time is short enough to avoid the color distortion and help the precise control of the gray scale.

• Advances in nano research
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• v.3 no.1
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.187-190
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• 1999

We have developed fabrication processes that form a wide-head T-gate with a 0.2 ${\mu}{\textrm}{m}$ gate length using the combination of thickness of each PMMA layer, line doses and development times for applications in millimeter- and micro-waves monolithic integrated circuits. The three-layer resist structure (PMMA/P(MMA-MAA)/PMMA = 1800 $\AA$/5800 A/1900$\AA$), 4nC/cm and over development were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. The experimented results show that the cross sectional area of T-gate fabricated by the proposed method is easily enlarged without additional processes.

• Transactions on Electrical and Electronic Materials
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• v.12 no.5
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• pp.197-199
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• 2011

In this paper, the bottom-gate thin-film transistors (TFTs) were fabricated with an amorphous/microcrystalline Si double layer (DL) as an active layer and the variations of the electrical characteristics were investigated according to the DC bias stresses. Since the fabrication process of DL TFTs was identical to that of the conventional amorphous Si (a-Si) TFTs, it creates no additional manufacturing cost. Moreover, the amorphous/microcrystalline Si DL could possibly improve stability and mass production efficiency. Although the field effect mobility of the typical DL TFTs is similar to that of a-Si TFTs, the DL TFTs had a higher reliability with respect to the direct current (DC) bias stresses.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1549-1551
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• 2002

현재 게이트 길이가 100nm 이하의 MOSFET 소자를 구현할 때 가장 대두되는 문제인 short channel effect를 억제하는 방법으로 제안된 소자 중 하나가 double gate (DG) silicon-on-insulator (SOI) MOSFET이다. 그러나 DG SOI MOSFET는 두 게이트간의 align과 threshold voltage control 문제가 있다. 본 논문에서는 DG SOI MOSFET에서 이상적으로 게이트가 align된 구조와 back 게이트가 front 게이트보다 긴 non-align된 구조가 subthreshold 동작 영역에서 impact ionization에 미치는 영향에 대해 시뮬레이션을 통하여 비교 분석하였다. 그 결과 게이트가 이상적으로 align된 구조보다 back 게이트가 front 게이트보다 긴 non-align된 구조가 게이트와 드레인이 overlap된 영역에서 impact ionization이 증가하였으며 게이트가 각각 n+ 폴리실리콘과 p+ 폴리실리콘을 가진 소자에서 두 게이트가 같은 work function을 가진 소자보다 높은 impact generation rate을 가짐을 알 수 있었다.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Journal of Sensor Science and Technology
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• v.5 no.4
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• pp.41-46
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• 1996

The Pd/Pt gate MISFET type hydrogen sensors, for detecting dissolved hydrogen gas in the transformer oil, were fabricated and their characteristics were investigated. These sensors including diffused resister heater and temperature monitoring diode were fabricated on the same chip by a conventional silicon process technique. The differential pair plays a role in minimizing the intrinsic voltage drift of the MISFET. To avoid the drift of the sensors induced by the hydrogen, the gate insulators of both FETs were constructed with double layers of silicon dioxide and silicon nitride. In order to eliminate the blister formation on the surface of the hydrogen sensing gate metal, Pt and Pd double metal layers were deposited on the gate insulator. The hydrogen response of the Pd/Pt gate MISFET suggests that the proposed sensor can detect the dissolved hydrogen in transformer oil with 40mV/10ppm of sensitivity and 0.14mV/day of stability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).