• Journal of Sensor Science and Technology
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• v.30 no.2
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• pp.82-87
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• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.11
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• pp.2621-2626
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• 2013

This paper has presented the potential distribution for asymmetric double gate(DG) MOSFET, and sloved Poisson equation to obtain the analytical solution of potential distribution. The symmetric DGMOSFET where both the front and the back gates are tied together is three terminal device and has the same current controllability for front and back gates. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine current controllability for front and back gates. To approximate with experimental values, we have used the Gaussian function as doping distribution in Poisson equation. The potential distribution has been observed for gate bias voltage and gate oxide thickness and channel doping concentration of the asymmetric DGMOSFET. As a results, we know potential distribution is greatly changed for gate bias voltage and gate oxide thickness, especially for gate to increase gate oxide thickness. Also the potential distribution for source is changed greater than one of drain with increasing of channel doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.691-694
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• 2013

This paper has presented the potential distribution for asymmetric double gate(DG) MOSFET, and sloved Poisson equation to obtain the analytical solution of potential distribution. The symmetric DGMOSFET where both the front and the back gates are tied together is three terminal device and has the same current controllability for front and back gates. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine current controllability for front and back gates. To approximate with experimental values, we have used the Gaussian function as charge distribution in Poisson equation. The potential distribution has been observed for gate bias voltage and gate oxide thickness and channel doping concentration of the asymmetric DGMOSFET. As a results, we know potential distribution is greatly changed for gate bias voltage and gate oxide thickness, especially for gate to increase gate oxide thickness. Also the potential distribution for source is changed greater than one of drain with increasing of channel doping concentration.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.7
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• pp.278-284
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• 1986

Double-diffused metal oxide power semiconductor field effect transistors are used extensively in recent years in various circuit applications. The temperature variation of the drain current at a fixed bias shows both positive and negative resistance characteristics depending on the gate threshold voltage and gate-to source bias votage. In this paper, the decision method of the gate crossover voltage by the temperature variation and a new method to determine the gate threshold voltage graphecally are presented.

• Journal of IKEEE
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• v.22 no.1
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• pp.74-79
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• 2018

We analyzed the relationship between center potential and subthreshold swing (SS) of Junctionless Cylindrical Surrounding Gate (JLCSG) and Junctionless Double Gate (JLDG) MOSFET. The SS was obtained using the analytical potential distribution and the center potential, and SSs were compared and investigated according to the change of channel dimension. As a result, we observed that the change in central potential distribution directly affects the SS. As the channel thickness and oxide thickness increased, the SS increased more sensitively in JLDG. Therefore, it was found that JLCSG structure is more effective to reduce the short channel effect of the nano MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.76-81
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• 2007

Threshold voltage ($V_{th}$) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ($x_h$) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.887-890
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• 2005

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin updoped Si channel for SCEs control, are being validated for sub-20nm scaling, A channel effects such as the subthreshold swing(SS), and the threshold voltage roll-off(${\Delta}V_{th}$). The propsed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1143-1148
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• 2014

This paper has analyzed the change of subthreshold swing for doping distribution function of asymmetric double gate(DG) MOSFET. The basic factors to determine the characteristics of DGMOSFET are dimensions of channel, i.e. channel length and channel thickness, and doping distribution function. The doping distributions are determined by ion implantation used for channel doping, and follow Gaussian distribution function. Gaussian function has been used as carrier distribution in solving the Poisson's equation. Since the Gaussian function is exactly not symmetric for top and bottome gates, the subthreshold swings are greatly changed for channel length and thickness, and the voltages of top and bottom gates for asymmetric double gate MOSFET. The deviation of subthreshold swings has been investigated for parameters of Gaussian distribution function such as projected range and standard projected deviation in this paper. As a result, we know the subthreshold swing is greatly changed for doping profiles and bias voltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.311-311
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• 2016

최근 고성능 디스플레이 개발이 요구되면서 기존 비정질 실리콘(a-Si)을 대체할 산화물 반도체에 대한 연구 관심이 급증하고 있다. 여러 종류의 산화물 반도체 중 a-IGZO (amorphous indium-gallium-zinc oxide)가 높은 전계효과 이동도, 저온 공정, 넓은 밴드갭으로 인한 투명성 등의 장점을 가지며 가장 연구가 활발하게 보고되고 있다. 기존에는 SG(단일 게이트) TFT가 주로 제작 되었지만 본 연구에서는 DG(이중 게이트) 구조를 적용하여 고성능의 a-IGZO 기반 박막 트랜지스터(TFT)를 구현하였다. SG mode에서는 하나의 게이트가 채널 전체 영역을 제어하지만, double gate mode에서는 상, 하부 두 개의 게이트가 동시에 채널 영역을 제어하기 때문에 채널층의 형성이 빠르게 이루어지고, 이는 TFT 스위칭 속도를 향상시킨다. 또한, 상호 모듈레이션 효과로 인해 S.S(subthreshold swing)값이 낮아질 뿐만 아니라, 상(TG), 하부 게이트(BG) 절연막의 계면 산란 현상이 줄어들기 때문에 이동도가 향상되고 누설전류 감소 및 안정성이 향상되는 효과를 얻을 수 있다. Dual gate mode로 동작을 시키면, TG(BG)에는 일정한 positive(or negative)전압을 인가하면서 BG(TG)에 전압을 가해주게 된다. 이 때, 소자의 채널층은 depletion(or enhancement) mode로 동작하여 다른 전기적인 특성에는 영향을 미치지 않으면서 문턱 전압을 쉽게 조절 할 수 있는 장점도 있다. 제작된 소자는 p-type bulk silicon 위에 thermal SiO2 산화막이 100 nm 형성된 기판을 사용하였다. 표준 RCA 클리닝을 진행한 후 BG 형성을 위해 150 nm 두께의 ITO를 증착하고, BG 절연막으로 두께의 SiO2를 300 nm 증착하였다. 이 후, 채널층 형성을 위하여 50 nm 두께의 a-IGZO를 증착하였고, 소스/드레인(S/D) 전극은 BG와 동일한 조건으로 ITO 100 nm를 증착하였다. TG 절연막은 BG 절연막과 동일한 조건에서 SiO2를 50 nm 증착하였다. TG는 S/D 증착 조건과 동일한 조건에서, 150 nm 두께로 증착 하였다. 전극 물질과, 절연막 물질은 모두 RF magnetron sputter를 이용하여 증착되었고, 또한 모든 patterning 과정은 표준 photolithography, wet etching, lift-off 공정을 통하여 이루어졌다. 후속 열처리 공정으로 퍼니스에서 질소 가스 분위기, $300^{\circ}C$ 온도에서 30 분 동안 진행하였다. 결과적으로 $9.06cm2/V{\cdot}s$, 255.7 mV/dec, $1.8{\times}106$의 전계효과 이동도, S.S, on-off ratio값을 갖는 SG와 비교하여 double gate mode에서는 $51.3cm2/V{\cdot}s$, 110.7 mV/dec, $3.2{\times}108$의 값을 나타내며 훌륭한 전기적 특성을 보였고, dual gate mode에서는 약 5.22의 coupling ratio를 나타내었다. 따라서 산화물 반도체 a-IGZO TFT의 이중게이트 구조는 우수한 전기적 특성을 나타내며 차세대 디스플레이 시장에서 훌륭한 역할을 할 것으로 기대된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.793-798
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• 2012

In this paper, dependence of subthreshold current has been analyzed for doping distribution and channel structure of double gate(DG) MOSFET. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. Since DGMOSFETs have reduced short channel effects with improvement of current controllability by gate voltages, subthreshold characteristics have been enhanced. The control of current in subthreshold region is very important factor related with power consumption for ultra large scaled integration. The deviation of threshold voltage has been qualitatively analyzed using the changes of subthreshold current for gate voltages. Subthreshold current has been influenced by doping distribution and channel dimension. In this study, the influence of channel length and thickness on current has been analyzed according to intensity and distribution of doping.