• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.490-493
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• 2002

In this study, we have investigated optimum value for side gate length and side gate voltage of double gate (DG) MOSFET with main gate and side gate. We know that optimum side gate voltage for each side length is about 3V. Also, we know that optimum side gate length for each main gate length is about 70nm. We have presented the transconductance and subthreshold slope for each side gate length. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.661-663
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• 2004

In this paper, we have investigated characteristics of C-V for double gate MOSFET with main gate and side gate by the variation of side sate length and side gate voltage. Main gate voltage is changed from -5V to +5V. We know that characteristics of C-V is good under the condition of LSG=70nm, VSG=3V, VD=2V. We have analyze characteristics of device by ISE-TCAD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.777-779
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• 2003

In this paper, we have investigated Characteristics of C-V for Double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated characteristics of C-V and main gate voltage is changed from -5V to ＋5V. Also we have investigated characteristics of C-V for DG MOSFET when the side gate length is changed from 40nm to 90nm. As the side gate length is reduced, the transconductance is increased and the capacitance is reduced. When the side gate voltage is 3V, we know that C-V curves are bending at near the main gate voltage of 1.8V. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.693-695
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• 2003

In this paper, we have investigated temperature-dependent characteristics of current-voltage for double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated the temperature-dependent characteristics of current-voltage and drain voltage is changed from 0V to 5.0V at $V_{mg}$ =1.5V and $V_{sg}$ =3.0V. We have obtained a very good characteristics of current-voltage for 77K. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.261-263
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• 2002

CMOS devices have scaled down to sub-50nm gate to achieve high performance and high integration density. Key challenges with the device scaling are non-scalable threshold voltage( $V^{th}$ ), high electric field, parasitic source/drain resistance, and $V^{th}$ variation by random dopant distribution. To solve scale-down problem of conventional structure, a new structure was proposed. In this paper, we have investigated double-gate MOSFET structure, which has the main-gate and the side-gates, to solve these problem.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.690-692
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• 2003

In this paper, we have investigated characteristics of radio frequency for double gate MOSFET with 50nm main gate in according to variation of side gate length. We could know the increasement of cut-off frequency as the side gate length is lower. As a result, we could know the most optimum performance characteristics when side gate length was 70nm. In this time, the DG MOSFET of side gate with 70nm has very high cut-off frequency like 41.4GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.486-489
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• 2002

In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.27-31
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• 2004

Models and simulations of gate tunneling current for thinoxide MOSFETs and Double-Gate SOIs are discussed. A guideline in design of leaky MOS capacitors is proposed and resonant gate tunneling current in DG SOI simulated based on quantum-mechanicalmodels. Gate tunneling current in fully-depleted, double-gate SOI MOSFETs is characterized based on quantum-mechanical principles. The simulated $I_G-V_G$ of double-gate SOI has negative differential resistance like that of the resonant tunnel diodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.16-24
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• 2009

Independent-gate-mode double-gate(IGM-DG) MOSFET overcomes the limitation of 3-terminal device structure, and enables to operate with different voltages for front-gate and back-gate. Therefore, circuit designs becomes not only simple, but also area-efficient due to the controllability of the 4th terminal provided by IGM-DG MOSFETs. In this paper, an RF receiver utilizing IGM-DG MOSFETs is presented and also, the circuit performance is verified by the HSPICE simulations. Besides, the circuit analysis and optimization are performed for various IGM-DG characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.498-501
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator. DG MOSFET have the main gate length of nm and the side gate length of 70nm. Then, we have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nino scale.