• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.139-144
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• 2016

This paper describes functional circuits of DC-DC converter IC incorporated with variable frequency PFM technique. In case of output voltage of DC-DC converter is reached setting value or output current is low then PFM switching frequency is slow down. In this work a PFM signal generator, a PFM Frequency Control Circuit, an output voltage detector and an over current protection circuits are designed. This device has been designed at a $0.35[{\mu}m]$, double poly, double metal 12[V] CMOS process.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.1
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• pp.1-7
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• 2012

This paper describes the performance comparison results for current controller of a single-phase PFC converter with 1-switch voltage doubler strategy for single-phase double-conversion UPS(Uninterruptible Power Supply). A single-phase PFC converter with 1-switch voltage doubler strategy needs a diode bridge and one bidirectional active switch. Thus it is possible to reduce the material cost. However, the study results of current controller design and comparison of current control method has not been known after the converter circuit was proposed. For the performance comparison of current control, single-phase 3 kVA double-conversion UPS was tested. The performance of PI and PR current controller is experimentally confirmed with followings - input current reference tracking, input power factor correction and input current THD suppression.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.45-48
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• 2001

An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.3
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• pp.122-128
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• 2012

An interleaved boost converter has many advantages such as current ripple reduction, switching effective double, etc. Due to these advantages, the interleaved boost converter applies to the power factor correction circuit. However, there are almost no analysis results because the input voltage and current are time-varying system in the power factor correction application. Therefore, in this paper, the current ripples of the power factor correction circuit using single-phase boost dc-dc converter and 2-phase interleaved boost dc-dc converter are compared and analyzed in detail. In order to verify the validity, computer simulation and experimental are performed.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.235-237
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• 2006

This paper proposes a DC-DC converter which is able to charge and discharge secondary batteries. The converter operates as a double-ended forward converter in charging process and as electrical isolated boost converter in discharging process. The converter is designed for continuous current operation. The switching frequency is selected as 100kHz to reduce the size of both the inductor and the capacitor.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1052-1054
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• 2001

This paper describes a boost converter to be operated at the boundary of continuous current mode(CCM) and discontinuous current mode(DCM) for power factor correction and low cost. A control method to be utilized in simulation is a average-current mode method in case of operating in CCM. The simulation results show that Better is the CCM converter then the DCM converter in harmonic content and input current waveform. And A Double-boost converter is superior to single-boost converter for input-current harmonic.

• Proceedings of the KIEE Conference
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• 2004.07e
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• pp.14-16
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• 2004

This paper describes a boost converter to be operated at the boundary of continuous current mode(CCM) and discontinuous current mode(DCM) for power factor correction and low cost. A control method to be utilized in simulation is a average Current mode method in case of operating in CCM. The simulation results show that Better is the CCM converter then the DCM converter in harmonic content and input current waveform. And A Double-boost converter is superior to single-boost converter for input-current harmonic.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1A
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• pp.85-90
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• 2008

Effects of the emitter degeneration on linearity have been investigated in SiGe HBT double-balanced up-converters with the Gilbert-cell structure. The emitter-coupled degeneration resistors have been optimized for high P1-dB and IP3 through the nonlinear harmonic-balance simulation. Two types of up-converter MMICs fabricated in $0.35{\mu}m$ Si-BiCMOS process were measured to verify the simulation results. The up-converter without the degeneration resistors produces a P1-dB of -13 dBm with an OIP3 of 3.7 dBm, while the up-converter with the degeneration resistors produces a P1-dB of -10 dBm with an OIP3 of 8.7 dBm.