• 제목/요약/키워드: Doping width

검색결과 92건 처리시간 0.029초

Tc and Jc distribution in in situ processed MgB2 bulk superconductors with/without C doping

  • Kim, C.J.;Kim, Y.J.;Lim, C.Y.;Jun, B.H.;Park, S.D.;Choo, K.N.
    • 한국초전도ㆍ저온공학회논문지
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    • 제16권2호
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    • pp.36-41
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    • 2014
  • Temperature dependence of magnetic moment (m-T) and the magnetization (M-H) at 5 K and 20 K of the in situ processed $MgB_2$ bulk pellets with/without carbon (C) doping were examined. The superconducting critical temperature ($T_c$), the superconducting transition width (${\delta}T$) and the critical current density ($J_c$) were estimated for ten test samples taken from the $MgB_2$ bulk pellets. The reliable m-T characteristics associated with the uniform $MgB_2$ formation were obtained for both $MgB_2$ pellets. The $T_cs$ and ${\delta}Ts$ of all test samples of the undoped $MgB_2$ were the same each other as 37.5 K and 1.5 K, respectively. The $T_cs$ and ${\delta}Ts$ of the C-doped $MgB_2$ were 36.5 K and 2.5 K, respectively. Unlike the m-T characteristics, there existed the difference among the M-H curves of the test samples, which might be caused by the microstructure variation. In spite of the slight $T_c$ decrease, the C doping was effective in enhancing the $J_c$ at 5 K.

측면산화 프리크리닝의 최소화를 통한 DRAM의 데이터 유지시간 개선 (Enhancement of Data Retention Time in DRAM through Optimization of Sidewall Oxidation Precleaning)

  • 채용웅;윤광렬
    • 한국전자통신학회논문지
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    • 제7권4호
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    • pp.833-837
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    • 2012
  • SC1(Standard Cleaning) 시간을 줄여 STI 측벽에서의 실리콘 손실 및 과도절개를 최소화하여 DRAM에서의 데이터 유지시간을 증가시키는 방법을 제안한다. SC1 시간 최적화를 통해 STI 상층 모서리부에서의 기생 전기장을 약화시킴으로서 Inverse Narrow Width 효과를 감소시키면 셀 트랜지스터의 Subthreshold 누설의 증가없이 채널 도핑농도가 감소하게 된다. 이것은 셀 접합에서 P-Well간 공핍 영역에서의 전기장을 최소화하여 일드나 데이터 유지시간의 증가를 보여 주었다.

Synthesis of p-Type ZnO Thin Film Prepared by As Diffusion Method and Fabrication of ZnO p-n Homojunction

  • Kim, Deok Kyu
    • 한국전기전자재료학회논문지
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    • 제30권6호
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    • pp.372-375
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    • 2017
  • ZnO thin films were deposited by RF magnetron sputtering and then diffused by using an As source in the ampouletube. Also, the ZnO p-n homojunction was made by using As-doped ZnO thin films, and its properties were analyzed. After the As doping, the surface roughness increased, the crystal quality deteriorated, and the full width at half maximum was increased. The As-doped ZnO thin films showed typical p-type properties, and their resistivity was as low as $2.19{\times}10^{-3}{\Omega}cm$, probably because of the in-diffusion from an external As source and out-diffusion from the GaAs substrate. Also, the ZnO p-n junction displayed the typical rectification properties of a p-n junction. Therefore, the As diffusion method is effective for obtaining ZnO films with p-type properties.

Spice parameter를 이용한 IGBT의 과도응답 예측 (Prediction of the transient response of the IGBT using the Spice parameter)

  • 이효정;홍신남
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.815-818
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    • 1998
  • The Insulated Gate Bipolar Transistor has the characteristics of MOSFET and BJT. The characteristics of proposed device exhibit high speed switching, the voltage controlled property, and the low ON resistance. This hybrid device has been used and developed continuously in the power electronic engineering field. We can simulate many IGBT circuits, such as the motor drive circuit, the switching circuits etc, with PSpice. However, some problems in PSpice is that the IGBT is old-fashioned and is very difficult to get it. In this paper, the IGBT in PSpice is considered as the basic structure. We changed the valuse of base width, gate-drain overlaping area, device area, and doping concentration, then calculated MOS transconductance, ambipolar recombination lifetime etc. Using this resultant parameter, we could predict the transient response characteristicsof IGBT, for examplex, voltage overshoot, the rising curve of voltage, and the falling curve of current.

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Current Modeling for Accumulation Mode GaN Schottky Barrier MOSFET for Integrated UV Sensors

  • Park, Won-June;Hahm, Sung-Ho
    • 센서학회지
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    • 제26권2호
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    • pp.79-84
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    • 2017
  • The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

원통형 접합경계를 갖는 punchthrough 다이오드의 항복전압에 대한 해석적 계산 (Analytical Calculation for the Breakdown Voltage of the Punchthrough Diode with Cylindrical Junction Edge)

  • 김두영;김한수;최연익;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 하계학술대회 논문집 C
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    • pp.1448-1450
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    • 1994
  • The breakdown voltages of punchthrough-mode diodes with cylindrical junction are analytically calculated, The proposed method, which is based on th Gauss's law, estimates the lateral expansion of the depletion region as well as the electric field and the charge distribution. The proposed method is given in terms of epitaxial layer width, the epitaxial layer doping concentration, and curvature radius of the junction edge. The calculation results agree well with the MEDICI simulation results for various device parameters.

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고전압 사이리스터 제작을 위한 Computer Simulation (Computer Simulation for High Voltage Thyristor Fabrication)

  • 김상철;김은동;김남균;방욱
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.243-246
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    • 2001
  • Thyristor devices have 3-dimensional complicated structure and were sensitive to temperature characteristics. Therefore, it was difficult to optimize thyristor devices design. We have to consider many design parameter to characterize, and trade-off relations. The important parameters to design thyristor devices are cathode structure, effective line width, cathode-emitter shunt structure, gate structure, doping profile and carrier lifetime. So, we must consider that these design parameters were not acted separately. However, there are many difficulties to determine optimized design parameters by experiment. So, We used specific design software to design thyristor devices, and estimated the thyristor devices characteristics.

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Design of 100-V Super-Junction Trench Power MOSFET with Low On-Resistance

  • Lho, Young-Hwan;Yang, Yil-Suk
    • ETRI Journal
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    • 제34권1호
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    • pp.134-137
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    • 2012
  • Power metal-oxide semiconductor field-effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double-diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. To overcome the tradeoff relationship, a super-junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on-state resistance of 1.2 $m{\Omega}-cm^2$ at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.

AlGaAs/GaAs double-heterojunction 전력용 FET의 설계 (Design of an AlGaAs/GaAs Double-Heterojunction Power FET)

  • 박인식;김상명;신석현;이진구;신재호;김도현
    • 전자공학회논문지A
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    • 제30A권8호
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    • pp.57-62
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    • 1993
  • In this paper, both feasible power gain and power added efficiency at the operating center frequency of 12 GHz are stressed to design a power FET with double-heterjunction structure. The variable parameters or the design are the unit gate width, the gate length, the doping density of AlGaAs, the AlGaAs thickness, the spacer thickness, the Al mole fraction, and the GaAs well thickness. The results of simulation for the FET with 1.mu.m gate length show that the power gain and the power added efficiency are 10.2 dB and 36.3% at 12GHz, respectively. An extrapolation of the relation between current gain and unilateral gain yields a 17 GHz cutoff frequency and 43GHz maximum frequency of oscillation. The calculation of the current versus voltage characteristics show that the output power of the device is about 0.62W.

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고 내압 전력 소자 설계를 위한 필드 링 최적화에 관한 연구 (Optimal Design of Field Ring for Power Devices)

  • 강이구
    • 전기전자학회논문지
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    • 제14권3호
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    • pp.199-204
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    • 2010
  • 본 논문에서는 전력반도체의 내압을 유지하는데 있어서 가장 중요한 필드 링의 개선을 위해 새로운 구조의 필드 링을 제안하였다. 제안한 트렌치 필드 링은 기존의 일반 필드 링에 비해 10%이상 효율을 개선하였다. 트렌치 필드 링의 설계를 위해 5가지의 변수를 두고 최적화 시뮬레이션을 수행하였으며, 수행한 파라미터 결과를 가지고 마스크를 설계하여 제작을 진행하였다. 내압이 증가하면 증가할 수록 트렌치 필드링이 일반 필드 링보다 더 좋은 결과를 가져올 수 있었다. 이러한 결과는 앞으로 전력반도체 소자인 IGBT, Power MOS 및 MCT 소자의 설계에 충분히 활용할 수 있을 것으로 판단된다.