• Title/Summary/Keyword: Distributed Arithmetic

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Optimization Design Method for Inner Product Using CSHM Algorithm and its Application to 1-D DCT Processor (연산공유 승산 알고리즘을 이용한 내적의 최적화 및 이를 이용한 1차원 DCT 프로세서 설계)

  • 이태욱;조상복
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.2
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    • pp.86-93
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    • 2004
  • The DCT algorithm needs an efficient hardware architecture to compute inner product. The conventional design method, like ROM-based DA(Distributed Arithmetic), has large hardware complexity. Because of this reason, a CSHM(Computation Sharing Multiplication) was proposed for implementing inner product by Park. However, the Park's CSHM has inefficient hardware architecture in the precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we presents the optimization design method for inner product using CSHM algorithm and applied it to implementation of 1-D DCT processor. The experimental results show that the proposed multiplier is more efficient than Park's when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using proposed design method is more high performance than typical methods.

Design on Pipeline Architecture for the Low and Column Address Generator of 2D DCT/IDCT (2D DCT/IDCT의 행, 열 주소생성기를 위한 파이프라인 구조 설계)

  • 노진수;박종태;문규성;성해경;이강현
    • Proceedings of the Korea Multimedia Society Conference
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    • 2003.05b
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    • pp.14-18
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    • 2003
  • This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50% up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

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Variable Radix-Two Multibit Coding and Its VLSI Implementation of DCT/IDCT (가변길이 다중비트 코딩을 이용한 DCT/IDCT의 설계)

  • 김대원;최준림
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.12
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    • pp.1062-1070
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    • 2002
  • In this paper, variable radix-two multibit coding algorithm is presented and applied in the implementation of discrete cosine transform(DCT) and inverse discrete cosine transform(IDCT). Variable radix-two multibit coding means the 2k SD (signed digit) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. This paper introduces the suggested algorithm, it's proof and the implementation of DCT/IDCT The implemented IDCT chip with 8 PEs(Processing Elements) and one transpose memory runs at a tate of 400 Mpixels/sec at 54MHz frequency for high speed parallel signal processing, and it's verified in HDTV and MPEG decoder.

A Design of high throughput IDCT processor in Distrited Arithmetic Method (처리율을 개선시킨 분산연산 방식의 IDCT 프로세서 설계)

  • 김병민;배현덕;조태원
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.6
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    • pp.48-57
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    • 2003
  • In this paper, An 8${\times}$l ID-IDCT processor with adder-based distributed arithmetic(DA) and bit-serial method Is presented. To reduce hardware cost and to improve operating speed, the proposed 8${\times}$1 ID-IDCT used the bit-serial method and DA method. The transform of coefficient equation results in reduction in hardware cost and has a regularity in implementation. The sign extension computation method reduces operation clock. As a result of logic synthesis, The gate count of designed 8${\times}$1 1D-IDCT is 17,504. The sign extension processing block has gate count of 3,620. That is 20% of total 8${\times}$1 ID-IDCT architecture. But the sign extension processing block improves more than twice in throughput. The designed IDCT processes 50Mpixels per second and at a clock frequency of 100MHz.

A Study on Evaluation for the Han River Water Quality Index (한강의 수질지수 산정에 관한 연구)

  • 서정현
    • Water for future
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    • v.14 no.3
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    • pp.55-66
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    • 1981
  • The theory and practice of water quality scoring and indexing are introduced. The monthly water analysis data are available for six stations long the down-stream Han River whthin the areal boundary of the Special City of Seoul. The data cover the period between 1975 and 1979 inclusive and contain the analytical findings on 37 water constituents including DO, BOD, temperature, total solids and etc. Sic parameters are selected form the 37 items, that, to the judgement of the writer, best reflect the water quality of the Han River. They are; dissolved oxggen saturation, pH, fecal coliform, total solids, BOD and nitrate+ammonia. For each of the six parameters, a subscore function is developed and graphically presented to facilitate the transform of a measurment of the arameter to a subscore on a common score(e.G. 0-100) The score of a sample is calculated as a fuction of the six subscores, using four different approaches; (1) the unweighted arithmetic water quality score, (2) the weighted arithmetic water quality score, (3)the unweighted multiplicative score and (4) the reduced (total) score. Independent of these calculated scores, the experts' score which is calculated by averaging the ratings of water quality experts is obtained and compared with each of the four calculated scores by means of the least square method. The experts' score compares most favorably with the "reduced" score with the correlation coefficient of 0.956 : therefore this method of water quality scoring is adopted to calculate the Han River water quality scores and indices. Water quality index data for Guiri, ukdo, Pokwangdong, Noryangjin, Yongdungpo and Kayang Stations, 1975-1979 are as follow: The overall water quality index data of the Han River between Guiri and Kayang Stations are found; 47.3 in 1976, 48.0 in 1977, 48.5 in 1978 and 54.7 in 1979, indicating the general trend towards water quality improvent in this part of the river, in terms of the increased water quality index by average 1.85 points per year during this period. Finally the optimum sampling frequencies distributed among the six stations, using an equation which takes into account the coefficients of variation of the water quality scores and indices arec calculated.alculated.

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2-D DCT/IDCT Processor Design Reducing Adders in DA Architecture (DA구조 이용 가산기 수를 감소한 2-D DCT/IDCT 프로세서 설계)

  • Jeong Dong-Yun;Seo Hae-Jun;Bae Hyeon-Deok;Cho Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.3 s.345
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    • pp.48-58
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    • 2006
  • This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

Wide Area Distribution of Nitrogen Concentrations in Mountain Streams of Hyogo Prefecture, Japan

  • Muramatsu, K.;Komai, Y.;Umemoto, S.;Inoue, T.
    • Environmental Engineering Research
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    • v.15 no.2
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    • pp.111-115
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    • 2010
  • To study the relationship between the concentrations of nitrogen in mountain streams, and anthropologic and natural factors, the water chemistry of the mountain streams in the entire Hyogo Prefecture, Japan, were investigated. A thousand mountain streams were investigated between 1998 and 2001. The concentrations of nitrate nitrogen ranged from 2.92 to 0.1 mg/L, with an arithmetic mean value of 0.45 mg/L. A number of streams showing more than 1.0 mg/L of nitrate nitrogen accounted for 8% of the mountain streams investigated. These results indicated that the concentrations of nitrate nitrogen in the mountain streams were low in the entire Hyogo Prefecture. In general, the mountain stream water in Hyogo Prefecture appears to not have been affected by wet and dry deposition originating from anthropologic sources in mountain streams and Japan. On the other hand, sites with more than 0.8 mg/L nitrate nitrogen were distributed over the entire Hyogo Prefecture, which were classified into five groups. Each group showed unique geographical, geological and anthropological characteristics. No common characteristic among five groups were discover. These results suggest that the cause of high concentrations of nitrogen in mountain streams is not from a uniform set of conditions.

Speech Interactive Agent on Car Navigation System Using Embedded ASR/DSR/TTS

  • Lee, Heung-Kyu;Kwon, Oh-Il;Ko, Han-Seok
    • Speech Sciences
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    • v.11 no.2
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    • pp.181-192
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    • 2004
  • This paper presents an efficient speech interactive agent rendering smooth car navigation and Telematics services, by employing embedded automatic speech recognition (ASR), distributed speech recognition (DSR) and text-to-speech (ITS) modules, all while enabling safe driving. A speech interactive agent is essentially a conversational tool providing command and control functions to drivers such' as enabling navigation task, audio/video manipulation, and E-commerce services through natural voice/response interactions between user and interface. While the benefits of automatic speech recognition and speech synthesizer have become well known, involved hardware resources are often limited and internal communication protocols are complex to achieve real time responses. As a result, performance degradation always exists in the embedded H/W system. To implement the speech interactive agent to accommodate the demands of user commands in real time, we propose to optimize the hardware dependent architectural codes for speed-up. In particular, we propose to provide a composite solution through memory reconfiguration and efficient arithmetic operation conversion, as well as invoking an effective out-of-vocabulary rejection algorithm, all made suitable for system operation under limited resources.

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Design and Implementation of Low-Power DWT Processor for JPEG2000 Compression of Medical Images (의료영상의 JPEG2000 압축을 위한 저전력 DWT 프로세서의 설계 및 구현)

  • Jang Young-Beom;Lee Won-Sang;Yoo Sun-Kook
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.54 no.2
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    • pp.124-130
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    • 2005
  • In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

Impact of Vegetation Heterogeneity on Rainfall Excess in FLO-2D Model : Yongdam Catchment (용담댐 유역에서 식생 이질성이 FLO-2D 유량 산정에 미치는 영향)

  • Song, Hojun;Lee, Khil-Ha
    • Journal of Environmental Science International
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    • v.28 no.2
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    • pp.259-266
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    • 2019
  • Two main sources of data, meteorological data and land surface characteristics, are essential to effectively run a distributed rainfall-runoff model. The specification and averaging of the land surface characteristics in a suitable way is crucial to obtaining accurate runoff output. Recent advances in remote sensing techniques are often being used to derive better representations of these land surface characteristics. Due to the mismatch in scale between digital land cover maps and numerical grid sizes, issues related to upscaling or downscaling occur regularly. A specific method is typically selected to average and represent the land surface characteristics. This paper examines the amount of flooding by applying the FLO-2D routing model, where vegetation heterogeneity is manipulated using the Manning's roughness coefficient. Three different upscaling methods, arithmetic, dominant, and aggregation, were tested. To investigate further, the rainfall-runoff model with FLO-2D was facilitated in Yongdam catchment and heavy rainfall events during wet season were selected. The results show aggregation method provides better results, in terms of the amount of peak flow and the relative time taken to achieve it. These rwsults suggest that the aggregation method, which is a reasonably realistic description of area-averaged vegetation nature and characteristics, is more likely to occur in reality.