Design on Pipeline Architecture for the Low and Column Address Generator of 2D DCT/IDCT

2D DCT/IDCT의 행, 열 주소생성기를 위한 파이프라인 구조 설계

  • 노진수 (조선대학교 전자정보통신공학부 MSI Lab.) ;
  • 박종태 (춘해대학) ;
  • 문규성 (조선대학교 전자정보통신공학부 MSI Lab.) ;
  • 성해경 (한양여자대학) ;
  • 이강현 (조선대학교 전자정보통신공학부 MSI Lab.)
  • Published : 2003.05.01


This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50% up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.