• 제목/요약/키워드: Dissipation current

검색결과 448건 처리시간 0.025초

Research for the interface circuit to reduce static current and rising time (접속 속도 향상 및 전력소모를 줄인 위성용 접속회로 연구)

  • Won, Joo-Ho;Ko, Hyoung-Ho
    • Journal of Satellite, Information and Communications
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    • 제11권3호
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    • pp.114-118
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    • 2016
  • In this paper, we present the advanced open collector circuit, interface circuit between aerospace electronics. Satellite is composed of a number of electronics, which were provided from various manufacturers. Each company manufactured its own electronics for satellite using its heritage and requirements for their electronics. Therefore each electronics may use different internal supplies. It make a problem between electronics because the supply is different from other electronics, such as the increasing of power dissipation because of the static current and the mismatch of interface voltage, the offset. Proposed circuit can reduce the static current and rising time, and also decrease the useless power dissipation caused by the static current for open collector circuit

Realization of 3.3V active low-pass filter using improved continuous-time current-mode CMOS integrator (개선된 연속시간 전류모드 CMOS 적분기를 이용한 3.3V 능동 저역필터 구현)

  • 방준호;조성익;이성룡;권오신;신홍규
    • Journal of the Korean Institute of Telematics and Electronics B
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    • 제33B권4호
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    • pp.52-62
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    • 1996
  • In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analog current-mode active filters was proposed. Compared to the current-mode integrator which was proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter was designed with the proposed current-mode integrator. The designed circuits were fabricated using the ORBIT's 1.2.mu.m double-poly double-metal CMOS n-well process. The experimental resutls of the active filter designed and fabricated for this research have shown that it has the performance of 44.5MHz cutoff frequency, 3.3mW power dissipation and the third-order active filter area was 0.12mm$^{2}$.

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Numerical simulation of electrokinetic dissipation caused by elastic waves in reservoir rocks

  • Zhang, Xiaoqian;Wang, Qifei;Li, Chengwu;Sun, Xiaoqi;Yan, Zheng;Nie, Yao
    • Geomechanics and Engineering
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    • 제19권1호
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    • pp.11-20
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    • 2019
  • The use of electrokinetic dissipation method to study the fluid flow law in micro-pores is of great significance to reservoir rock microfluidics. In this paper, the micro-capillary theory was combined with the coupling model of the seepage field and the current field under the excitation of the harmonic signal, and the coupling theory of the electrokinetic effect under the first-order approximation condition was derived. The dissipation equation of electrokinetic dissipation and viscous resistance dissipation and its solution were established by using Green's function method. The physical and mathematical models for the electrokinetic dissipation of reservoir rocks were constructed. The microscopic mechanism of the electrokinetic dissipation of reservoir rock were theoretically clarified. The influencing factors of the electrokinetic dissipation frequency of the reservoir rock were analyzed quantitatively. The results show that the electrokinetic effect transforms the fluid flow profile in the pores of the reservoir from parabolic to wavy; under low-frequency conditions, the apparent viscosity coefficient is greater that one and is basically unchanged. The apparent viscosity coefficient gradually approaches 1 as the frequency increases further. The viscous resistance dissipation is two orders of magnitude higher than the electrokinetic effect dissipation. When the concentration of the electrolyte exceeds 0.1mol/L, the electrokinetic dissipation can be neglected, while for the electrolyte solution (<$10^{-2}M$) in low concentration, the electrokinetic dissipation is very significant and cannot be ignored.

Properties of a Hybrid Type Superconducting Fault Current Limiter using YBa2Cu3O7 Films (YBa2Cu3O7 박막을 이용한 하이브리드형 초전도 사고전류제한기의 특성)

  • Choi, Hyo-Sang;Cho, Yong-Sun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • 제19권4호
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    • pp.391-397
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    • 2006
  • We present investigations of a hybrid type superconducting fault current limiter (SFCL), which consists of transformers and resistive superconducting elements. The secondary windings of the transformer were separated into several electrically isolated circuits and linked inductively with each other by mutual flux, each of which has a superconducting current limiting element of $YBa_2Cu_3O_7$ (YBCO) stripes as a current limiting element. Simple connection in series of the SFCL elements tends to produce ill-timed quenching because of power dissipation unbalance between SFCL elements. Both electrical isolation and mutual flux linkage of the elements provides a solution to power dissipation unbalance, inducing simultaneous quench and current redistribution of the YBCO films. This design enables to increase the voltage rating of SFCL with given YBCO stripes.

Design of a programmable current-mode folding/interpolation CMOS A/D converter (프로그래머블 전류모드 폴딩 . 인터폴레이션 CMOS A/D 변환기 설계)

  • 김형훈
    • Proceedings of the IEEK Conference
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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    • pp.45-48
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    • 2001
  • An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

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A novel approach for designing of variability aware low-power logic gates

  • Sharma, Vijay Kumar
    • ETRI Journal
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    • 제44권3호
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    • pp.491-503
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    • 2022
  • Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

Optimal design of HTS current lead considering natural convection (자연대류를 고려한 초전도 전류도입선의 최적 설계)

  • 손봉준;설승윤
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 한국초전도저온공학회 2003년도 추계학술대회 논문집
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    • pp.269-273
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    • 2003
  • In this paper the HTS current lead for superconducting device is studied numerical method. The current lead is cooled by surrounded He gas by natural convection. To find wall heat flux, the linearization method is adopted Numerical results using natural convection cooling are compared with conventional cooling methods such as conduction cooling and vapor cooling. The results shows that the minimum heat dissipation is much smaller than conduction cooling. Also, the minimum heat dissipation is obtained for the non-zero gradient of temperature at warm end. HTS current lead operating current sharing mode is reduce heat flow to superconducting system.

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Design of a CMOS Programmable Slew Rate Operational Amplifier with a Switched Parallel Current Subtraction Circuit (병렬전류감산기를 이용한 슬루율 가변 연산증폭기 설계)

  • 신종민;윤광섭
    • Journal of the Korean Institute of Telematics and Electronics B
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    • 제32B권5호
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    • pp.730-736
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    • 1995
  • This paper presents the design of a CMOS programmable slew rate operational amplifier based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. By utilizing the newly designed circuit, it was proven that slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 5. 83V/$\mu$s to 41.4V/$\mu$s, power dissipation ranging from 1.13mW to 4.1mW, and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.

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High performance and low power sense amplifier design for SONOS flash memory (SONOS 플래시 메모리용 저전력 고성능 Sense amplifier 설계)

  • Jung Jin-Gyo;Jung Young-Wook;Jung Xong-Ho;Kwack Kae-Dal
    • Proceedings of the IEEK Conference
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.469-472
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    • 2004
  • In this paper a current mode sense amplifier suitable for 30nm SONOS flash memories read operation is presented. The proposed sense amplifier employs cross coupled latch type circuit and current mirror to amplify signal from selected memory cell. This sense amplifier provides fast response in low voltage and low current dissipation. Simulation results show the sensing delay time and current dissipation for power supply voltages Vdd to expose limitations of the sense amplifier in various operating conditions.

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Characteristics of 15 kVA Superconducting Fault Current Limiters Using Thin Films (15 kVA급 박막형 초전도 전류제한기의 한류특성)

  • 최효상;현옥배;김혜림;황시돌
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • 제13권12호
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    • pp.1058-1062
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    • 2000
  • We investigated resistive superconducting fault current limites (SFCLs) fabricated using YBCO thin films on 2-inch diameter sapphire substrates. Nearly identical SFCL units were prepared and tested. The units were connected in series and parallel to increase the current and voltage ratings. A serial connection of the units showed significantly unbalanced power dissipation between the units. This imbalance was removed by introducing a shunt resistor to the firstly quenched unit. Parallel connection of the units increased the current rating. An SFCL module of 4 units in parallel, each of which has minimum quench current rating. An SFCL module of 4 units in parallel, each of which has minimum quench current 25 A$\_$peak/, was produced and successfully tested at a 220 V$\_$rms/circuit. From the resistance increase, we estimated that the film temperature increased to 200 K in 5 msec, and 300 K in 120 msec. Successive quenches revealed that this system is stable without degradation in the current limiting capability under such thermal shocks as quenches at 220 V$\_$rms/.

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