• 한국운동역학회지
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• 제22권3호
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• pp.315-324
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• 2012

The purpose of current study was to investigate the effects of the heights on the lower extremities, torso and neck segments for energy dissipation during single-leg drop landing from different heights. Twenty eight young healthy male subjects(age: $23.21{\pm}1.66yr$, height: $176.03{\pm}4.22cm$, weight: $68.93{\pm}5.36kg$) were participated in this study. The subjects performed the single-leg drop landing from the various height(30, 45 & 60 cm). Force plates and motion-capture system were used to capture ground reaction force and kinematics data, respectively. The results were as follows. First, the ROM at the ankle, knee, hip and trunk was increased with the increased heights but the ROM at the neck was increased in the 60cm. Second, the angular velocity, moment and eccentric work at the ankle, knee, hip, trunk, and neck was increased with the increased heights. Third, the contribution to total work at the knee joint was not significantly different, while the ankle joint rate was decreased and hip and neck rate was increased in the 60cm, and trunk rate was increased with the increased heights. Lastly, the increase in landing height was able to augment the level of energy dissipation not only at the lower extremities but also at the trunk and neck. The findings showed that drop landing affect trunk and neck with lower extremity joints. Therefore, we need to consider that trunk and neck strengthening including stability should be added to reduce sports injury during prevention training.

• Current Research on Agriculture and Life Sciences
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• 제31권4호
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• pp.272-279
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• 2013

사과 중 triazole계 살균제 flusilazole 및 myclobutanil의 생물학적 반감기와 출하전 잔류허용기준을 산출하기 위해 안전사용기준에 근거한 기준량과 3배량의 약제를 살포하고 그 잔류량을 조사하였다. 시험기간 중 두 농약의 잔류량은 각각의 MRL 이하로 나타났으며, 사과 중 생물학적 반감기는 flusilazole의 경우 기준량 처리구에서 6.7일, 3배량 처리구에서 6.2일로 나타났다. 반면에 myclobutanil의 반감기는 기준량 처리구에서 13.3일, 3배량 처리구에서 24.8일로 나타나 flusilazole보다 더 긴 반감기를 가지는 것으로 조사되었다. First order kinetics에 근거한 감소지수식을 이용하여 산출된 각 농약의 감소상수는 flusilazole에 대하여 0.0513, myclobutanil에 대하여 0.0244이었으며, 산출된 감소상수들을 이용하여 출하 전 잔류허용기준(PHRL)을 계산한 결과, 안전사용기준을 준수한 농약살포를 가정하였을 때 flusilazole은 수확 일주일 전 0.43 mg/kg, myclobutanil은 같은 시기 0.59 mg/kg 이하로 잔류하면 수확 시 잔류농도가 MRL 이하로 잔류할 것으로 예측된다.

• 한국전기전자재료학회논문지
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• 제21권7호
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• pp.652-659
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• 2008

The nonlinear electrical properties and aging characteristics against surge stress of ZPCCL-based varistors were investigated for different sintering temperatures of the range $1240-1300^{\circ}C$. As the sintering temperature increased, the varistor voltage decreased from 732.2 to 53.8 V/mm, the nonlinear exponent decreased from 58.5 to 4.1, and the leakage current increased from $0.38{\mu}A$ to $46.5{\mu}A$. The varistors sintered at $1250^{\circ}C$ and $1260^{\circ}C$ exhibited the high stability against multiple surge, $150A/cm^2(8{\times}20{\mu}s)$. On the whole, the variation rate of electrical characteristics against impulse current stress was gradually increased in order of varistor voltage$\rightarrow$nonlinear exponent$\rightarrow$dissipation facto$\rightarrow$leakage current.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2001년도 학술대회 논문집
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• pp.84-88
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• 2001

The optimum cross-sectional area Profile of gas-cooled high-temperature superconductor (HTS) current lead is analyzed to have minimum helium boil-off rate. The conventional constant area HTS lead has much higher helium consumption than the optimum HTS lead considered in this study. The optimum HTS lead has variable cross-sectional area to have constant safety factor. An analytical formula of optimum shape of lead and temperature profile are obtained. For multi-step HTS current leads, the optimum tape lengths and minimum heat dissipation rate are also formulated. The developed formulations are applied to the Bi-2223 material, and the differences between constant area, constant safety-factor, and multi-step current leads are discussed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권7호
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• pp.315-319
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• 2003

We improved quench properties of a superconducting fault current limiter (SFCL) based on YBCO thin films by their serial and parallel combinations. The SFCL consisted of 6 switching elements fabricated of 4 inch-diameter YBCO thin films. The quench currents of the switching elements were distributed between 33.9 A and 35.6 A. Simple serial connection resulted in imbalanced power dissipation between switching elements even at the quench current difference of 0.6 A. On the other hand, $2{\times}2$ and $3{\times}2$ stack combinations produced simultaneous quenches. The $3{\times}2$ stack combination showed better simultaneous quench behavior than the $2{\times}2$ stacks. This is suggested to be because the currents between switching elements in parallel connection of the $3{\times}2$ stacks were more effectively redistributed than the $2{\times}2$ stacks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.66-69
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• 2004

This work is the study of Voltage-Down Converter used as internal supply voltage having large current driving and stable voltage level at any variation of process, voltage, and temperature(P.V.T). It converts VDD(external supply voltage) into $V_{1NT}(internal\;supply\;voltage).$ From the simulation results, a new Voltage-Down Converter has large current driving and a little stand-by current under lower supply voltage than conventional circuit. And bad characteristic of VINT, peaking, was eliminated. Start-up circuit for BGR is also added to one circuit, which consumes less current dissipation than convention circuit

• 대한전자공학회논문지SD
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• 제39권8호
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• pp.42-45
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• 2002

낮은 전력선 잡음과 피드쓰루 전류를 갖는 저전력 SDRAM 출력 버퍼가 소개된다. 다수의 I/O를 갖는 SDRAM 출력 버퍼에 있어서, 제안된 언더슈트 방지 회로를 통하여, 피드쓰루 전류의 감소뿐 아니라, 전력소모의 감소가 가능하다. 효율적인 피드백 방법을 사용한 풀다운 드라이버를 사용하여, 접지선 잡음을 감소시킬 수 있다. 기존의 회로에 비하여 접지선 잡음은 66.3%, 순간 전력소모는 27.5%, 평균 전력 소모는 11.4% 감소되었다.

• 전자공학회논문지C
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• 제34C권6호
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.