• 제목/요약/키워드: Discrete Wavelet

검색결과 665건 처리시간 0.022초

Spatial Error Concealment Technique for Losslessly Compressed Images Using Data Hiding in Error-Prone Channels

  • Kim, Kyung-Su;Lee, Hae-Yeoun;Lee, Heung-Kyu
    • Journal of Communications and Networks
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    • 제12권2호
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    • pp.168-173
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    • 2010
  • Error concealment techniques are significant due to the growing interest in imagery transmission over error-prone channels. This paper presents a spatial error concealment technique for losslessly compressed images using least significant bit (LSB)-based data hiding to reconstruct a close approximation after the loss of image blocks during image transmission. Before transmission, block description information (BDI) is generated by applying quantization following discrete wavelet transform. This is then embedded into the LSB plane of the original image itself at the encoder. At the decoder, this BDI is used to conceal blocks that may have been dropped during the transmission. Although the original image is modified slightly by the message embedding process, no perceptible artifacts are introduced and the visual quality is sufficient for analysis and diagnosis. In comparisons with previous methods at various loss rates, the proposed technique is shown to be promising due to its good performance in the case of a loss of isolated and continuous blocks.

Fast Hybrid Transform: DCT-II/DFT/HWT

  • 쉬단핑;신태철;단위;이문호
    • 방송공학회논문지
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    • 제16권5호
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    • pp.782-792
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    • 2011
  • In this paper, we address a new fast DCT-II/DFT/HWT hybrid transform architecture for digital video and fusion mobile handsets based on Jacket-like sparse matrix decomposition. This fast hybrid architecture is consist of source coding standard as MPEG-4, JPEG 2000 and digital filtering discrete Fourier transform, and has two operations: one is block-wise inverse Jacket matrix (BIJM) for DCT-II, and the other is element-wise inverse Jacket matrix (EIJM) for DFT/HWT. They have similar recursive computational fashion, which mean all of them can be decomposed to Kronecker products of an identity Hadamard matrix and a successively lower order sparse matrix. Based on this trait, we can develop a single chip of fast hybrid algorithm architecture for intelligent mobile handsets.

실시간 내장형 응용을 위한 2차원 웨이브렛 변환 프로세서 (2D DWT Processor for Real-time Embedded Applications)

  • 정갑천;박성모
    • 전자공학회논문지CI
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    • 제40권2호
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    • pp.17-25
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    • 2003
  • 본 논문에서는 상태 변수 표현 방법에 따른 알고리즘 분할을 통해 2차원 웨이브렛 변환 연산을 실시간으로 처리할 수 있는 프로세서 구조를 제안하였다. 제안된 프로세서 구조는 영상입력에 대하여 행, 열 방향을 동시에 고려하여 데이터 플로우 방식으로 처리함으로써 중간적인 결과의 메모리 저장 및 읽기에 소요되는 전달 지연 시간을 감소할 수 있어 실시간 처리에 적합한 VLSI 구조이다. 필터의 길이를 K라할 때 프로세서는 내부에 4개의 곱셈기, 4개의 덧셈기 및 NK-N 크기의 메모리를 가지는 등의 하드웨어 복잡도가 낮아 웹 카메라 서버와 같은 내장형의 응용에 매우 적합한 구조이고, 쉽게 어레이 구조로 확장할 수 있어 고성능을 요구하는 다양한 영상 처리 응용에도 사용 가능하다.

에지와 대역확산기술을 이용한 디지털 워터마킹 기법 (A New Watermarking Algorithm Using the Edge and PN Code)

  • 송상주;이두성
    • 한국컴퓨터정보학회논문지
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    • 제9권4호
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    • pp.13-18
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    • 2004
  • 본 논문은 디지털 콘텐츠 제작자에 대한 저작권관리(DRM:Digital Right Management)의 한 요소기술인 워터마크 기법으로서 주파수 공간에서의 이산웨이브릿변환을 사용하여 새로이 제안한 것이다. 본 논문에서 새로이 제안한 워터마크 삽입 및 검출 알고리즘은 에지와 스팩트럼확산 기술을 사용하여 워터마크 시퀀스를 생성하고, 이산웨이브릿 변환을 이용해서 구성하였다. 본 논문에서 제안한 방법에 대하여 여러 가지 공격을 시도한 결과 Lenna 영상을 이용한 cox의 유사도 측정값은 6이상이고, PSNR은 40dB 이상이었으며, JPEG과 COLLUSION, CLIPPING, SCALING 등에서 워터마크 기술의 다양한 평가기준에 만족하는 것을 보여주었으며, 무감지성, 강인성, 기밀성 그리고 디지틀 콘텐츠 유통의 안정성을 보장하는 방법으로서 타당함을 입증하였다.

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지진관측자료의 효과적인 활용에 관한 고찰 (Best Use of the Measured Earthquake Data)

  • 연관희;박동희;김성주;최원학;장천중
    • 한국지진공학회:학술대회논문집
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    • 한국지진공학회 2001년도 추계 학술발표회 논문집 Proceedings of EESK Conference-Fall 2001
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    • pp.36-43
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    • 2001
  • In Korea, we are absolutely short of earthquake data in good quality from moderate and large earthquakes, which are needed fur the study of strong ground motion characteristics. This means that the best use of the available data is needed far the time being. In this respect, several methods are suggested in this paper, which can be applied in the process of data selection and analysis. First, it is shown that the calibration status of seismic stations can be easily checked by comparing the spectra from accelerometer and velocity sensor both of which are located at the same location. Secondly, it is recommended that S/N ratio in the frequency domain should be checked before discarding the data by only look of the data in time domain. Thirdly, the saturated earthquake data caused by ground motion level exceeding the detection limit of a seismograph are considered to see if such data can be used for spectrum analysis by performing numerical simulation. The result reveals that the saturated data can still be used within the dominant frequency range according to the levels of saturation. Finally, a technique to minimize the window effect that distorts the low frequency spectrum is suggested. This technique involves detrending in displacement domain once the displacement data are obtained by integration of low frequency components of the original data in time domain. Especially, the low frequency component can be separated by using discrete wavelet transform among many alternatives. All of these methods mentioned above may increase the available earthquake data and frequency range.

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Minimum Statistics-Based Noise Power Estimation for Parametric Image Restoration

  • Yoo, Yoonjong;Shin, Jeongho;Paik, Joonki
    • IEIE Transactions on Smart Processing and Computing
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    • 제3권2호
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    • pp.41-51
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    • 2014
  • This paper describes a method to estimate the noise power using the minimum statistics approach, which was originally proposed for audio processing. The proposed minimum statistics-based method separates a noisy image into multiple frequency bands using the three-level discrete wavelet transform. By assuming that the output of the high-pass filter contains both signal detail and noise, the proposed algorithm extracts the region of pure noise from the high frequency band using an appropriate threshold. The region of pure noise, which is free from the signal detail part and the DC component, is well suited for minimum statistics condition, where the noise power can be extracted easily. The proposed algorithm reduces the computational load significantly through the use of a simple processing architecture without iteration with an estimation accuracy greater than 90% for strong noise at 0 to 40dB SNR of the input image. Furthermore, the well restored image can be obtained using the estimated noise power information in parametric image restoration algorithms, such as the classical parametric Wiener or ForWaRD image restoration filters. The experimental results show that the proposed algorithm can estimate the noise power accurately, and is particularly suitable for fast, low-cost image restoration or enhancement applications.

NDFT-based Image Steganographic Scheme with Discrimination of Tampers

  • Wang, Hongxia;Fan, Mingquan
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제5권12호
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    • pp.2340-2354
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    • 2011
  • A new and secure image steganographic scheme based on nonuniform discrete Fourier transform (NDFT) is proposed in this paper. First, the chaotic system is introduced to select embedding points randomly in NDFT domain suitable range, and NDFT is implemented on every non-overlapping block of eight consecutive pixels. Second, the secret messages are scrambled by chaotic systems, and embedded into frequency coefficients by quantization method. The stego-image is obtained by inverse NDFT (INDFT). Besides, in order to discriminate tampers, the low frequency wavelet coefficients of 7 most significant bits (MSBs) of the stego-image are converted into the binary sequence after nonuniform scalar quantization. Then the obtained binary sequence is scrambled by the chaotic systems, and embedded into the least significant bit (LSB) of the stego-image. Finally, the watermarked stego-image can be obtained by a new improved LSB steganographic method. The embedded secret messages can be extracted from the watermarked stego-image without the original cover image. Experimental results show the validity of the proposed scheme, and dual statistics attacks are also conducted to indicate the security.

ARM9 프로세서용 실시간 JPEG2000 코덱의 구현 (A Real-Time JPEG2000 Codec Implementation on ARM9 Processor)

  • 김영태;조시원;이동욱
    • 융합신호처리학회논문지
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    • 제8권3호
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    • pp.149-155
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    • 2007
  • 본 논문에서는 ARM9 프로세서를 위한 실시간 JPEG 2000 코덱을 구현하였다. 구현된 코덱은 프로세서, 메모리와 같은 시스템의 리소스를 효율적으로 사용할 수 있도록 제어 코드와 데이터 관리 코드를 분리하여 설계하였다. 특히 이동전화와 같은 임베디드 환경에서는 제한된 프로세서와 내부메모리를 이용하여 양질의 서비스를 제공하는 것이 매우 중요하다. ARM9계열의 프로세서는 부동소수점을 제공하지 않기 때문에 DWT와 같이 아주 반복적으로 부동소수점 연산을 필요로 하는 동작을 실행하기 위해서는 많은 연산시간이 필요하다. 제안된 코덱은 이러한 단점을 극복하기 위해 고정소수점을 이용하여 프로그램을 하였다. 또한 캐시 메모리를 고려한 코드 최적화 방법을 적용하여 연산속도를 더욱 향상시켰다.

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SoC를 위한 JPEG2000 IP 설계 및 구현 (JPEG2000 IP Design and Implementation for SoC Design)

  • 정재형;한상균;홍성훈;김영철
    • 한국방송∙미디어공학회:학술대회논문집
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    • 한국방송공학회 2002년도 정기총회 및 학술대회
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    • pp.63-68
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    • 2002
  • JPEG2000은 기존의 정지영상압축부호화 방식에 비해 우수한 비트율-왜곡(Rate-Distortion)특성과 향상된 주관적 화질을 제공하며 인터넷, 디지털 영상카메라, 이동단말기, 의학영상 등 다양한 분야에서 적용될 수 있는 새로운 정지영상압축 표준이다. 본 논문에서는 SoC(System on a Chip)설계를 고려한 JPEG2000 인코더의 구조를 제안하고 IP(Intellectual Property)를 설계 및 검증하였다. 구현된 JPEG2000 IP는 DWT(Discrete Wavelet Transform)블록, 스칼라양자화블록, EBCOT(Embedded Block Coding with Optimized Truncation)블록으로 구성되어 있다. IP는 모의실험을 통해 구현 구조에 대한 타당성을 검증하였고, 반도체설계자산연구센터에서 제시한 'RTL Coding Guideline'에 따라 HDL을 설계하였다. 특히, DWT블록은 구현시 많은 연산과 메모리 용량이 필요하므로 영상을 저장할 외부 메모리를 사용하였고, 빠른 곱셈과 덧셈연산을 위한 3단 파이프라인 부스곱셈기(3-state pipeline booth multiplier)와 캐리예측 덧셈기(carry lookahead adder)를 사용하였다. 설계된 JPEG2000 IP들은 삼성 0.35$\mu\textrm{m}$ 라이브러리를 이용하여 Synopsys사 Design Analyzer 틀을 통해 논리 합성하였으며, Xillinx 100만 게이트 FPGA칩에 구현하여 그 동작을 검증하였다. 또한, Hard IP 설계를 위해 Avanti사의 Apollo툴을 이용하여 Layout을 수행하였다.

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의료영상의 JPEG2000 압축을 위한 저전력 DWT 프로세서의 설계 및 구현 (Design and Implementation of Low-Power DWT Processor for JPEG2000 Compression of Medical Images)

  • 장영범;이원상;유선국
    • 대한전기학회논문지:시스템및제어부문D
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    • 제54권2호
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    • pp.124-130
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    • 2005
  • In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.