• Journal of computational fluids engineering
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• v.13 no.1
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• pp.1-6
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• 2008

Direct Write Technologies are being utilized in various industrial fields such as antennas, engineered structures, sensors and tissue engineering. With Direct Write Technologies, producing features have the mesoscale range, from 1 to 100 microns. One form of the Direct Write Technologies is based on aerosol dynamics. The shape of deposited aerosols determine the form of products in the Direct Write Technology based on aerosol dynamics. To predict shape of deposited aerosol, a prediction model is created. In this study, we estimated Line-Width and Line-Thickness from the prediction model. Results of prediction model is valid from comparison with experimental results.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.372-373
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• 2006

Modern business trends call for miniaturization of electronic systems. One of the major impedances in this miniaturization is the conductive and inductive components in chips and circuit boards. Direct Write Technology can write these soft magnetic materials, thus allowing for further miniaturization of inductor devices. Another obstacle in electronics fabrication is the size limitations of thick screen-printing and the material limitations in ink jet printing. Direct Write Technologies address both of these limitations by providing feature sizes less than 20 microns with a wide range of materials possibilities. A discussion of the application of these nano-particulate materials by Direct Write Technologies will be presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.783-787
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• 2000

A microprocessor, which is used as a CPU for state-of-the-art personal computers, adopts 256KB or 512KB L2(Level 2) cache memory. This cache hires Direct Mapping Procedure, 32B Line Size, and no Write Allocation. In this cache architecture, we can expert about 2.5% hit ratio improvement by using 8-way Set Associative Mapping instead of Direct Mapping, 128B Line Size instead of 32B, and Write Allocation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.335-336
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• 2012

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.65-70
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• 2024

Direct cache-to-cache transfer has been studied to reduce the latency and bandwidth consumption related to the shared data in multiprocessor system. Even though these studies lead to meaningful results, they assume that caches consist of SRAM. For example, if the system employs the non-volatile memory, the one of the most important parts to consider is to decrease the number of write operations. This paper proposes a hybrid write avoidance cache coherence protocol that considers the hybrid cache architecture. A new state is added to finely control what is stored in the non-volatile memory area, and experimental results showed that the number of writes was reduced by about 36% compared to the existing schemes.

• Journal of IKEEE
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• v.12 no.3
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• pp.138-143
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• 2008

In this study, we propose that the structures of spiral inductors have the environment advantage utilizing direct-write and LAM(Laser Ablation of Microparticles) processes without process step of lithography and etching etc. of existing semiconductor process. The structures of inductors have Si thickness of 540${\mu}m$, $SiO_2$ thickness of 3${\mu}m$. The width of Cu coils and the space between segments have 30${\mu}m$, respectively, using for direct-write and LAM processes. The performance of spiral planar inductors was simulated to frequency characteristics for inductance, quality-factor, SRF(Self- Resonance Frequency) using HFSS. The inductors without underpass and via have inductance of 1.11nH over the frequency range of 300 to 800 MHz, quality-factor of maximum 38 at 5 GHz, SRF of 18 GHz. Otherwise, inductors with underpass and via have inductance of 1.12nH over the frequency range of 300 to 800 MHz, quality-factor of maximum 35 at 5 GHz, SRF of 16 GHz.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.337-345
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• 2016

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.15 no.2
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• pp.1-8
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• 2016

Generally, electrical circuits are fabricated as Printed Circuit Boards (PCBs) and mounted on the casing of the product. Additionally, this requires many other parts and some labor for assembly. Recently, molding technology has increasingly been applied to embed simple circuits in plastic casing. The technology is called a Molded Interconnected Device (MID). By using this technology, PCB fabrication can be replaced by molding, and much of the corresponding assembly process for PCBs can be eliminated if the circuit is simple enough for molding. Furthermore, as the improvement of conductive materials and printing technologies of simple electric circuits can be printed directly on the casing part, this also reduces the complexity of the product design and production cost. Therefore, this paper introduces a new MID fabrication process using direct 3D printing technology. Additionally, it is applied to an automotive part of a cruise control switch. The methodology and design are shown.