• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.353-359
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• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

• Korean Journal of Computational Design and Engineering
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• v.8 no.2
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• pp.65-74
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• 2003

For virtual reality, virtual manufacturing system, or simulation based design, we need to visualize very large and complex 3D models which are comprising of very large number of polygons. To overcome the limited hardware performance and to attain smooth realtime visualization, there have been many researches about algorithms which reduce the number of polygons to be processed by graphics hardware. One of these algorithms, occlusion culling is a method of rejecting the objects which are not visible because they are occluded by other objects, and then passing only the visible objects to graphics hardware. Existing occlusion culling algorithms have some shortcomings such as the required long preprocessing time, the limitation of occluder shape, or the need for special hardware implementation. In this study, an efficient occlusion culling algorithm is proposed. The proposed algorithm reads and analyzes Z-buffer of graphics hardware using Microsoft DirectX, and then determines each object's visibility. This proposed algorithm can speed up visualization by reading Z-buffer using DirectX which can access hardware directly compared to OpenGL, by reading only the region to which each object is projected instead of reading the whole Z-Buffer, and the proposed algorithm can perform more exact visibility test by using simplified model instead of using bounding box. For evaluation, the proposed algorithm was applied to very large polygonal models. And smooth realtime visualization was attained.

• Journal of Korean Society on Water Environment
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• v.31 no.2
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• pp.166-180
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• 2015

Pollutant in watersheds comes from two major sources which are NPS (nonpoint source pollution) and PS (point source pollution). Most of the pollutant can be treated by wastewater treatment plants. However, wastewater treatment plants may not be an appropriate practice to improve water quality for the watersheds with large portion of NPS pollutant and NPS pollution from direct runoff and baseflow has different characteristics. Therefore the practices to improve water quality need to be comprehensive for pollutants by both direct runoff and baseflow. Riparian buffer, one of practices to manage pollutant in watershed, has been applied to reduce pollutant not only from direct runoff but also baseflow. In this study, the scenarios for pollutant reduction by wastewater treat plants and the nitrogen reduction by riparian buffer were simulated using SWAT-REMM to suggest an effective plan for pollutant reduction from baseflow. Riparian buffer provided nitrogen reduction of 0.2~75.0% in YbB watershed and 38.0~47.0% in GbA watershed. The result indicates that riparian buffer is effective to reduce the pollutant especially from baseflow, and it suggested as suitable for the a watershed which WWTP discharge is not capable to reduce enough pollutant.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.589-592
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• 1999

This paper describes direct $\mu$C-Si/CaF$_2$/glass thin film growth by RPCVD system in a low temperature for thin film transistor (TFT), photovoltaic devices. and sensor applications. Experimental factors in a low temperature direct $\mu$ c-Si film growth are presented in terms of deposition parameters: SiH$_4$/H$_2$ ratio, chamber total pressure, substrate temperature, rf power, and CaF$_2$ buffer layer. The structural and electrical properties of the deposited films were studied by means of Raman spectroscopy, I-V, L-I-V, X-ray diffraction analysis and SEM. we obtain a crystalline volume fraction of 61%, preferential growth of (111) and (220) direction, and photosensitivity of 124. We achieved the improvement of crystallinity and electrical property by using the buffer layers of CaF$_2$ film.

• Journal of Advanced Navigation Technology
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• v.20 no.1
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• pp.79-85
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• 2016

Network traffic is increased rapidly, due to mobile and social network, such as smartphones and facebook, in recent web environment. In this paper, we improved web response time of existing system using direct buffer of NIO and DMA. This solved the disadvantage of JAVA, such as CPU performance reduction due to the blocking of I/O, garbage collection of buffer. Key values circulated many data due to priority change put on a hash map operated easily and apply a priority modification algorithm. Large response data is separated and stored at a fast direct buffer and improved performance. This paper showed that the proposed method using NIO was much improved performance, in many test situations of cache hit and cache miss.

• Journal of the Korean Society of Visualization
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• v.18 no.3
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• pp.109-115
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• 2020

Five layers in mean flow are proposed by using the direct numerical simulation data of turbulent pipe flow up to Reτ = 3008. Viscous sublayer, buffer layer, mesolayer, log layer and core region are investigated. In the buffer layer, the viscous force is counterbalanced by the turbulent inertia from the streamwise mean momentum balance, and a log law occurs here. The overlap layer is composed of the mesolayer and the log layer. Above the buffer layer, the non-negligible viscous force causes the power law, and this region is the mesolayer, where it is the lower part of the overlap layer. At the upper part of the overlap layer, where the viscous force itself becomes naturally negligible, the log layer will appear due to that the acceleration force of the large-scale motions increases as the Reynolds number increases. In the core region, the velocity-defect form is satisfied with the power-law scaling.

• Journal of Korea Soil Environment Society
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• v.3 no.3
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• pp.3-10
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• 1998

Acid/Base buffer capacity of soil is very important in prediction of contaminant transport for its direct impact on pH change of the system composed of soil-contaminant-water, In this research, diffuse double layer theory as well as two layer electrostatic adsorption model are applied to develop a theoretical model of buffer capacity of soil. Model application procedures are presented as well. Buffer capacity of Georgia kaolinite and Milwhite kaolinite was measured by acid-base titration. Model prediction and experimental results are compared.

• Biotechnology and Bioprocess Engineering:BBE
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• v.5 no.6
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• pp.418-421
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• 2000

A new direct colorimetric assay of microcystin in water and algal samples is proposed consisting of two procedures as follows: 1) the elimination of phosphorus in the sample and concentration of microcystin using a C(sub)18 cartridge, 2) the detection of the released phosphorus by the ascorbic acid method and determination of protein phosphatase (PP) inhibition by microcystin. The optimum amounts of phosphorylase ${\alpha}$ and PP-1 in 50 ${\mu}$L concentrated sample were 50$\mu\textrm{g}$/50${\mu}$L buffer and 1.0unit/50${\mu}$L buffer, respectively, for the best assay. The pH for the maximum activity of PP-1 was 8. The minimum detectable concentration for this method was about 0.02$\mu\textrm{g}$/L, which is sufficient to meet the proposed guideline level of 1$\mu\textrm{g}$ microcystin/L in drinking water. Consequently, it would seem that the proposed direct colorimetric assay using PP is a rapid, easy, and convenient method for the detection of microcystin in water and algal samples.

• ETRI Journal
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• v.25 no.5
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• pp.275-287
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• 2003

We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.