ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Dual Cache Architecture for Low Cost and High Performance

  • Received : 2030.11.05
  • Published : 2003.10.31
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Abstract

We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.

Keywords

References

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