• 한국전기전자재료학회논문지
• /
• 제17권2호
• /
• pp.162-170
• /
• 2004

A 900MHz CMOS RF power amplifier with digitally controllable output power has been proposed and designed with 0.6${\mu}{\textrm}{m}$ standard CMOS technology. The designed power amplifier was composed of digitally controllable switch mode pre-amplifiers with an integrated 4nH spiral inductor load and class-C output stage. Especially, to compensate the 1ow Q of integrated spiral inductor, cascode amplifier with a Q-enhancement circuit is used. It has been shown that the proposed power control technique allows the output power to change from almost 3dBm to 13.5dBm. And it has a maximum PAE(Power Added Efficiency) of almost 55％ at 900MHz operating frequency and 3V power supply voltage.

• 한국전자파학회논문지
• /
• 제25권8호
• /
• pp.795-801
• /
• 2014

본 논문에서는 2.6 GHz에 설계된 고출력 전력증폭기에 DDBS(Digitally-controlled Dynamic Bias Switching)를 적용하여 평균 전력에서 효율을 개선하였다. DBS는 제어 신호에 따라 전력 증폭기에 두 단계의 드레인 전압을 인가하여 효율을 개선하는 기술이다. DBS의 제어 신호를 디지털로 처리하여 제어가 매우 용이하였다. 2.6 GHz의 중심 주파수와 10 MHz 대역폭, 9.5 dB의 PAPR(Peak-to-Average Power Ratio)을 갖는 64 QAM FDD LTE 신호를 사용하여 측정한 결과, DDBS를 적용하여 전력증폭기의 PAE(Power-Added Efficiency)을 평균 전력 43 dBm에서 40.9 %에서 48 %로 증가시켰다.

• ETRI Journal
• /
• 제33권3호
• /
• pp.366-373
• /
• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.851-854
• /
• 1999

A high efficient, CMOS RF power amplifier at a 2.SV power supply for the band of 902-928MHz was designed and analyzed in 0.25${\mu}{\textrm}{m}$ standard CMOS technology. The output power of designed amplifier is being digitally controlled from a minimum of 2㎽ to a maximum of 21㎽, corresponding to a dynamic range of l0㏈ power control. The frequency response of this power amplifier is centered roughly at 915MHz. The power added efficiency of designed amplifer is almost 48% at maximum output power of 21㎽.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권3호
• /
• pp.198-206
• /
• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• ETRI Journal
• /
• 제33권2호
• /
• pp.201-209
• /
• 2011

This paper presents a wide-band fine-resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three-step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• 조명전기설비학회논문지
• /
• 제25권2호
• /
• pp.80-86
• /
• 2011

This paper presents an integrated variable amplitude high voltage pulse generation circuit with low power and small size for driving industrial piezoelectric printer heads. To solve the problems of large size and power overhead of conventional pulse generators that usually assembled with multiple high-cost discrete ICs on a PCB board, we have designed a new integrated circuit (IC) chip. Since all the functions are integrated on to a single-chip it can achieve low cost and control the high-voltage output pulse with variable amplitudes as well. It can also digitally control the rising and falling times of an output high voltage pulse by using programmable RC time control of the output buffer. The proposed circuit has been designed and simulatedd in a 180[nm] Bipolar-CMOS-DMOS (BCD) technology using HSPICE and Cadence Virtuoso Tools. The proposed single-chip pulse generation circuit is suitable for use in industrial printer heads requiring a variable high voltage driving capability.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2008년도 하계학술대회 논문집
• /
• pp.478-480
• /
• 2008

On this paper, digitally controlled push-pull dc-dc converter and dc-ac inverter for induction motor control are presented, which is used one DSP(digital signal processor). This system has 12V battery input for the push-pull converter, and the push-pull converter generates 300V output for induction motor inverter input. In order to compensate the push-pull converter, the transfer function of push-pull converter is derived and digital PI compensator is adapted. Through bode diagram, stability of digital controlled push-pull converter is analyzed. To verify the proposed system, digital simulation of the induction motor drive using digital push-pull converter are performed.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2008년도 하계학술대회 논문집
• /
• pp.598-600
• /
• 2008

On this paper, digitally controlled flyback dc-dc converter and dc-ac inverter for bldc motor control are presented, which is used one processor. This system has 12V battery input for the flyback-converter, and the flyback-converter generates 30V output for BLDC motor inverter input. In order to compensate the flyback-converter, the transfer function of flyback converter is derived and digital PI compensator is adapted. Through bode diagram, stability of digital flyback-converter is analyzed. To verify the proposed system, digital simulation of the bldc motor drive using digital flyback-converter are performed.

• 전기전자학회논문지
• /
• 제24권4호
• /
• pp.1074-1080
• /
• 2020

본 논문은 공정, 전압 및 온도에 둔감하며, 출력전압 상태에 따라 3가지 동작모드가 가능한 디지털 제어 벅 변환기를 제안한다. 기존 디지털 제어 방식의 벅 변환기는 A/D 변환기, 카운터 및 딜레이 라인 회로를 사용하여서 정확한 출력 전압을 제어하였다. 정확한 출력 전압 제어를 위해서는 카운터 및 딜레이 라인 비트 수를 증가시켜서 회로 복잡성 증가 문제점을 지니고 있다. 이러한 회로의 복잡성 문제를 해결하기 위해서 제안된 회로에서는 8비트 및 16 비트 양 방향 쉬프트 레지스터를 사용하고 최대 128비트 해상도까지 듀티비 제어가 가능한 벅 변환기를 제안한다. 제안하는 벅 변환기는 CMOS 180 나노 공정 1-poly 6-metal을 사용하여 설계 및 제작하였으며, 2.7V~3.6V의 입력 전압과 0.9~1.8V의 출력 전압을 생성하고, 리플전압은 30mV, 전력 효율은 최대 92.3%, 과도기 응답속도는 4us이다.