• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1701-1705
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• 2004

This paper presents a design and analysis of electromechanical sigma-delta modulator for MEMS gyroscope, which enables us to control the proof mass and to obtain an exact digital output without additional A/D conversion. The system structure and the circuit realization of the sigma-delta modulation are simpler than those of the analog sensing and feedback circuit. Based on the electrical sigma-delta modulator theory, a compensator is designed to improve the closed loop resolution of the sensor. With the designed compensator, we could obtain enhanced closed-loop performances of the gyroscope such as larger bandwidth, lower noise, and digital output comparing with the results of analog open-loop system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.96-100
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• 2015

Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a ${\sum}{\Delta}$ ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at $10^{-6}$ BER increased from 0.261 UI to 0.363 UI with stable loop convergence.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1296-1297
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• 2011

This paper deals with a power-hardware-in-the loop simulation (PHILS) of permanent magnet synchronous generator (PMSG) type wind power generation system (WPGS) using a real hardware which consists of a motor generator set with motor drive, real time digital simulator (RTDS), and back-to-back converter. A digital signal processor (DSP) controls the back-to-back converter connected between the back-to-back converter and the RTDS. The proposed PHILS can effectively be applied to demonstrate the operational characteristics of PMSG type WPGS under grid connection.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.55-64
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• 1997

Spread Spectrum Communication is a core technique in CDMA system, but the problem for SS Communication schemes is synchronous method. There are DLL, Tau-dither, SO etc, in the synchronous method. But since there are analog operations, the settling is difficult and size is large. In this paper we realized Digital Delay Lock Loop (DDLL) and estimated it's performance through the Power line experiment.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.548-552
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• 1987

The constraint condition of the loop filter is persented for the convergence of the random jitter accumulation fo the 2-nd order PLL (phase-locked loop) circuit used in digital regenerative repeater. This condition is confirmed under the assumption that the number of repeater chain is 5, bandwidth is 100. 0KHz, the power spectral density of white Gaussian noise is 1.0x10**-6 [W/Hz]. Also, it is shown that if the condition is satisfied, the accumulated random jitter and the alignment jitter will have the saturation characteristics.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.830-835
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• 1998

This paper describes a new digital control method of 3-phase PWM inverter with LC filter for uninterruptible power supply(UPS). The overall control system is based on the dead beat control, which has the minor loop of current control within the voltage control major loop. In this paper, the full-order disturbance observer is proposed to compensate the disturbances generated due to a sudden change of load currents. The proposed disturbance observer is composed of dead beat observer which estimates state values within a finite time, and cancels the disturbances by adding feedforward compensation loop in the control system. In addition, on order to remove a defect of oscillation generated in output of conventional dead beat controller, a modified dead beat algorithm is proposed in this paper.

• Journal of Communications and Networks
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• v.7 no.3
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• pp.248-257
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• 2005

In this paper, we develop design procedures for carrier tracking loop for orthogonal frequency division multiplexing (OFDM) systems or other systems of blocked data. In such communication systems, phase error measurements are made infrequent enough to invalidate the traditional loop design methodology which is based on analog loop design. We analyze the degradation in the OFDM schemes caused by the tracking loop and show how the performance is dependent on the rms phase error, where we distinguished between the effect of the variance in the average phase over the symbol and the effect of the phase change over the symbol. We derive the optimal tracking loop including optional delay in the loop caused by processing time. Our solution is general and includes arbitrary phase noise apd additive noise spectrums. In order to guarantee a well behaved solution, we have to check the design against margin constraints subject to uncertainties. In case the optimal loop does not meet the required margin constraints subjected to uncertainties, it is shown how to apply a method taken from control theory to find a controller. Alternatively, if we restrict the solution to first or second order loops, we give a simple loop design procedure which may be sufficient in many cases. Extensions of the method are shown for using both pilot symbols and data symbols in the OFDM receiver for phase tracking. We compare our results to other methods commonly used in OFDM receivers and we show that a large improvement can be gained.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.184-188
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• 2001

In this paper, a new fully digital control method for single-phase UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. The inner current control loop is designed and implemented in the form of internal model control and takes the presence of computational time-delay into account. Therefore, this method provides an overshoot-free reference-to-output response. In the proposed scheme, the outer voltage control loop employing P controller with resonance model implemented by a DSP is introduced. The proposed resonance model has an infinite gain at resonant frequency, and it exhibits a function similar to an integrator for AC component. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been demonstrated by the simulation and experimental results respectively.

• International Journal of Computer Science & Network Security
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• v.23 no.7
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• pp.23-31
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• 2023

This article discusses the sabotage of loops of intruder alarm systems. Although loop alarm systems are now gradually being replaced by digital alarm systems, they are still significantly present in practice. This paper describes two experimentally verified techniques for sabotaging balanced loops. The first technique is based on the jump replacement of the balancing resistor by a fake resistor. The second technique is based on inserting a series-parallel combination of two rheostats into the loop. By alternately changing the resistance of these rheostats, a state is reached where the balancing resistor is shorted by the parallel rheostat and replaced by the series rheostat. Sabotage devices for both attacks are technically simple and inexpensive, so they can be made and used by an amateur. Owners of loop alarm systems should become find out about this threat.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.1-11
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• 2007

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.