• 한국전자파학회논문지
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• 제22권2호
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• pp.258-264
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• 2011

본 논문은 GSM(Global System for Mobile communications)에서 주로 사용되는 Offset-PLL(Phase Locked Loop) 방식을 사용하여 낮은 위상 잡음과 빠른 위상 고정 시간, 우수한 불요파 특성을 갖는 주파수 합성기를 설계 제작하였다. 제안된 주파수 합성기의 구조는 3번의 주파수 하향 변환을 통해 낮은 위상 잡음 갖도록 하였으며, 높은 주파수 해상도를 갖도록 세 개의 offset 주파수중 최종 offset 주파수를 DDS(Direct Digital Synthesizer)를 이용하여 생성하였다. 또한, 빠른 스위칭 속도를 가질 수 있도록 DAC(Digital to Analog Converter)를 사용하였다. DAC 사용에 따른 위상 잡음 열화를 줄이기 위해 DAC 노이즈 제거를 위한 필터를 설계하여 성능을 개선하였다.

• 전기학회논문지
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• 제63권4호
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• pp.559-564
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• 2014

A microgrid as a small scale power system is operated by the grid-connected mode and islanded mode. It is anticipated that the battery energy storage system (BESS) is able to be applied to the microgrid for stable power control, such as tie-line and smoothing control in the grid-connected mode and voltage and frequency control in the islanded mode. In this paper, a digital signal processor (DSP), Two BESS controllers based on TMS320F28335 of a microgrid are implemented and are tested to show control performance in the hardware-in-the loop simulation (HILS) system.

• 제어로봇시스템학회논문지
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• 제21권2호
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• pp.168-172
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• 2015

In general, open-loop fiber-optic gyroscopes (FOG) are less stable than closed-loop FOGs but they offer simpler implementation. The typical operation time of line-of-sight (LOS) stabilization systems is a few seconds to one hour. In this paper, a open-loop fiber optic gyroscope (FOG) for LOS applications is designed and implemented. The design goal is aimed at implementing a low cost, compact FOG with low Angle Random Walk (ARW) (< $0.03deg/\sqrt{h}$) and bias instability (< 0.25deg/h). The FOG uses an open-loop all-fiber configuration with 100M PM fiber wound on a small diameter spool. In order to get the design goal, digital signal processing techniques for signal detection, modulation control and compensation are designed and implemented in FPGA.

• 전기학회논문지
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• 제63권3호
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• pp.343-348
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• 2014

Recently, applications of VSC-HVDC systems to power systems are growing because of their control ability of reactive power. Meanwhile, the hardware-in-the-loop simulation (HILS) based on the real-time digital simulator has been applying to develop and test imbedded controllers and systems in the power industry to decrease costs and to save time. In this paper, a 3-level neutral point clamped (NPC) VSC-HVDC system is modeled and the embedded controllers of the NPC VSC-HVDC system are designed. The designed controllers are implemented by TMS320F28335. The TMS320F28335-based controllers of the NPC VSC-HVDC system are tested using the HILS.

• 한국통신학회논문지
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• 제26권10B호
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• pp.1464-1469
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• 2001

본 논문에서는 디지털 하이브리드 위상고정루프(Digital Hybrid Phase-Locked Loop, DHPLL) 주파수 합성기 구조에서 고 순도 스펙트럼과 초고속 스위칭 속도를 위한 설계기술을 제안한다. D/A 변환기 출력으로 전압제어발진기(Voltage Controlled Oscillator, VCO)를 구동하는 개 루프(open-loop) 구성 방식과 기존 위상고정루프(Phase Locked Loop, PLL)의 폐 루프(closed-loop) 구성 방식을 혼합한 하이브리드 구조의 주파수 합성기를 고려하여, 시스템 변수(개 루프 대역과 위상 여유)와 성능 파라미터(정착시간, 위상 잡음, 그리고 최대 오버슈트(Max. overshoot)의 관계를 연구하였다. 그리고 이 관계를 통해 스펙트럼 순도와 스위칭 속도를 향상시키기 위한 최적의 3가지 설계방안을 제시한다. 컴퓨터 시뮬레이션 결과, 주파수 스위칭 과정에서 발생하는 최대 오버슈트가 0.0991%이고 완전 정상상태 도달시간은 0.288msec이다. offset 주파수 10KHz에서 위상 잡음은 -128.15dBc이다.

• International Journal of Control, Automation, and Systems
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• 제5권1호
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• pp.35-42
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• 2007

This paper presents an INS(Inertial Navigation System) grade, surface micro-machined differential resonant accelerometer(DRXL) manufactured by an epitaxially grown thick poly silicon process. The proposed DRXL system generates a differential digital output upon an applied acceleration, in which frequency transition is measured due to gap dependent electrical stiffness change. To facilitate the resonance dynamics of the electromechanical system, the micromachined DRXL device is packaged by using the wafer level vacuum sealing process. To test the DRXL performance, a nonlinear self-oscillation loop is designed based on the extended describing function technique. The oscillation loop is implemented using discrete electronic elements including precision charge amplifier and hard feedback nonlinearity. The performance test of the DRXL system shows that the sensitivity of the accelerometer is 24 Hz/g and its long term bias stability is about 2 mg($1{\sigma}$) with dynamic range of ${\sigma}70g$.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.219-224
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• 1996

Piezoelectric actuators exhibit limited accuracy in tracking control due to their hysteresis nonlinearity. In this study a digital tracking control approach for a piezoelectric actuator based on incorporating a feedback linearization loop with a PID feedback controller is presented. The hysteresis nonlinearity of the piezoelectric actuator is modeled in the feedback compensation loop using the Maxwell slip model. Experiments were performed on a piezoelectric 2-axis linear positioner for tracking linearly decaying sinusoidal waveforms and circles. The experimental results show that the tracking control performance is noticeably improved by augmenting the feedback loop with a model of hysteresis in the feedback compensation loop.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.2
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• pp.223-228
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• 2006

The main purpose of this paper is to describe the code tracking performance of a non-coherent digital delay lock loop (DLL) or coherent DLL while tracking GNSS signal in the presence of signal masking. The masking effect is usually caused by buildings that obscure the signal in either a periodic or random manner. In some cases, ideal masking is used to remove random or periodic interference. Three types of the masked signal are considered - no masking, periodic masking, and random masking of the signal input to the receiver. The mean time to lose lock (MTLL) of the code tracking loop are evaluated, and some numerical result and simulation results are reported. Finally, the steadystate tracking errors on the performance of the tracking loop in interference environment are also presented.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• 한국통신학회논문지
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• 제35권12C호
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• pp.1029-1034
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• 2010

QPSK 디지털 수신기는 전송 경로 또는 송수신기 간의 클럭 차이에 의해 발생하는 위상 편차를 보정하기 위해 위상 복원 방안이 필요하다. 널리 사용되고 있는 디지털 Costas 위상 복원 루프는 입력신호의 주파수/위상 복원 성능이 입력 신호의 전력에 따라 달라지므로 별도의 자동 이득조정 (AGC) 루프가 필요하고, 이는 하드웨어 구현시 시스템의 복잡도와 사용 자원을 증가시킨다. 본 논문에서는 입력 전력에 관계없이 일정한 위상 보정 기능을 수행할 수 있으며 타이밍 복원을 위한 AGC를 동시에 제공할 수 있는 위상 보정 및 진폭 보상 방안을 제안하였다. 제안된 방안은 CORDIC 알고리즘을 사용하여 입력 신호의 위상 및 진폭 정보를 분리하여 각각 처리하며 시스템의 복장도 및 사용 자원을 대폭 절감할 수 있으며, C++ 및 Model Sim을 사용한 모의실험을 통해 본 논문에서 제안한 위상 복원 루프의 동작을 검증하였다.