• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 1998년도 학술발표회논문집
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• pp.162-165
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• 1998

A certain degree of energy saving can be possible by controlling the delay time of occupancy sensor. In this paper a control circuit is designed for automatic control of delay time setting appropriate to different situations using a digital counter, two latches and an adder. The delay time is controlled by adjusting the time constant of RC circuit through on-off control of switching devices according to adder output, which determines the base current level of switching devices. And from PSpice simulation it is verified to function properly.

• 대한전자공학회논문지
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• 제13권6호
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• pp.1-6
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• 1976

탄성파 지연선의 진동자에서 전단과 지연매질사이의 접착제의 두께를 고려하여 변환손실을 계산하는 방법을 제안하며, 수치계산결과 접착제의 두께가 진동자 두께의 1/100정도 이하로 하여야 하며 전극의 두께가 진동자 두께의 1/10정도 될 때 중심주파수의 이동이 생진다. 접착제의 두께를 진동자와 거의 같거나 그 이상으로 하면 주파수 대역폭에서 현상이 점점 커지게 된다. In this paper, the methode of calculating conversion loss is proposed by considering the thickness of bonding medium between electrode and delay material in the vibrator of Elastic delay lines. As the result of computations using digital computer, it is shown that the thickness of bonding medium must be less than about 1/100 of the thickness of vibrator and when the thickness of electrode is about 1110 of vibrator, the center fnequency is shifted. When the thickness of bonding medium is equal to or more than the thickness of vibrator, the 리uctuations in frequency Bandwidth become larger and larger.

• 융합신호처리학회논문지
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• 제8권3호
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• pp.163-170
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• 2007

본 논문에서는 bicubic 방법보다 하드웨어 구조는 간단하면서 확대 이미지는 더욱 선명한 polyphase scaler를 제안하였다. 제안된 시스템은 새로운 픽셀을 얻기 위해서 디지털 필터의 group delay를 이용하여 해상도를 확대하는 방식을 사용하였으며 bicubic 방법과 비교하여 더 좋은 성능을 가지면서 하드웨어 구조를 간단히 하여 모바일 기기 등에 쉽게 적용이 가능하도록 설계하였다. 기존 polyhpase 필터는 해상도 확대시 영상을 흐릿하게 하는 blurring 노이즈가 발생하는 문제점을 가지고 있었다. 그래서 입력 신호의 고주파 성분을 증폭시키도록 Polyphase 필터를 boost-up 필터로 수정하여 보다 선명한 결과를 얻을 수 있었다. 본 논문에서 제안하는 polyphase scaler는 Xilinx Virtex2 FPGA를 이용하여 하드웨어 검증을 수행하였다. 제안된 polyphase scaler는 핸드폰 카메라의 디지털 줌으로 사용되어 질 수 있다.

• 한국통신학회논문지
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• 제21권1호
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.93-96
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• 2000

This paper has been proposed an audio DAC structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter on-a-chip. The passband ripple(< 0.41${\times}$fs), passband attenuation(at 0.41${\times}$fs) and stopband attenuation(> 0.59${\times}$fs) of the Δ$\Sigma$ modulator output using the proposed digital interpolation filter had ${\pm}$ 0.001 ［㏈］, -0.0025［㏈］ and -75［㏈］, respectively. Also the inband group delay was 30.07/fs［s］ and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20［㏈］ approximately at 65［㎑］, out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2593-2596
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• 2003

The deadbeat properties have been well known in designing digital control systems. But recently several researchers proposed a CDBC(Continuout-time DeadBeat Controller) in continuous time. They used delay or smoothing elements from the finite Laplace Transform. A delay element is made by the exponential terms. A smoothing element is used to smooth the digital control input. And eventually the process is argumentd with smoothing elements and then well-known digital deadbeat controller is designed Sometimes samplings are done in continuous time systems and some hold devices are used to relate to digital systems. So multirate sampling may enhance the efficiency of the CDBC. A DC servo motor is chosen for implementing CDBC algorithm. Especially Outputs according to the variable input and disturbance are simulated. by use of Matlab Simulink.

• 한국조명전기설비학회지:조명전기설비
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• 제8권2호
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• pp.41-45
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• 1994

본 논문은 MRA PWM 기법을 응용한 Sub-MRA PWM 기법을 디지털 신호 처리용 프로세서를 이용하여 구현하였다. Sub-MRA PWM기법을 디지털 신호처리 함으로서 아날로그의 불안정한 요소를 감소시킬 수 있었다. 이를 검증하기 위하여 시뮬레이션을 통하여 고조파를 분석하였다. 디지털 제어의 단점인 시간 지연은 고속 연산을 이용하여 극소화 할 수 있었다. 그러므로, 유도, 전동기를 실시간으로 제어할 수 있었다.

• 한국통신학회논문지
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• 제21권8호
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• pp.2043-2054
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• 1996

In this paper, Digital Delay Locked Loop(DDLL) is designed, implemented and analysed by experiment whose results show that it is possible to track the received signal by this scheme. Designed digital DLL has an advantage that it is not needed to maintain gain balance between early and late channels, which has been problem with an analog DLL. Also DDLL has more improved noise performance compared to analog DLL due to noise level limitation and noise cancellation characteristics. For various loop parameters, their effects on loop performance are analysed and simulated. Proposed DDLL is the first attempt as a digital approach in code tracking loop and it is expected to be a good reference for spread spectrum communication research.

• 한국멀티미디어학회논문지
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• 제25권2호
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• pp.325-334
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• 2022

Digital twin has the advantages of quality improvement and cost reduction, so it is widely applied to various industries. In this paper, a method to implement the major technologies of digital twin easily and quickly is presented. These include data management and relay servers, real-time monitoring applications including remote control interfaces, and direct connection protocols for video streaming. In addition, an algorithm for controlling a two-wheeled vehicle with a 2D interface is also proposed. The implemented system performs near real-time synchronization between the real environment and the virtual space. The delay time that occurs in remote control of the vehicle in the real environment was compared with the results of applying the proposed delay time reduction method. In addition, in the case of 2D interface-based control, an algorithm that can guarantee the user experience was implemented and applied to the actual environment and verified through experiments.

• 전자공학회논문지
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• 제51권9호
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• pp.182-189
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• 2014

탭 딜레이(tapped delay) 방식은 field-programmable gate arrary(FPGA) 내부 리소스를 이용한 설계에 적합하여 FPGA기반 시간-디지털 변환기(time-to-digital converter)로 널리 사용되고 있다. 그런데 이 방식의 시간-디지털 변환기에서는 지연 소자로 사용하는 전용 캐리체인(dedicated carry chain)의 탭 당 지연시간 차이가 정밀도 저하의 가장 큰 원인이 되고 있다. 본 논문에서는 일반적인 구형파 대신 고정된 시간 폭을 가지는 펄스신호를 지연 소자로 인가하고 상승과 하강 엣지에서 두 번의 시간 측정을 통해 전용 캐리체인내 지연시간의 불균일성을 보상하고 정밀도를 향상하는 시간-디지털 변환기 구조를 제안한다. 제안한 구조는 두 번의 시간 측정을 위해 2개 구역의 전용 캐리체인을 필요로 한다. Dual 엣지 보상 전 두 전용 캐리체인에서 탭 당 지연시간의 평균은 각각 17.3 ps, 16.7 ps에서 보상 후 평균은 11.2 ps, 10.1 ps으로 감소하여 각각 35%, 39% 이상 향상되었다. 가장 중요한 탭 당 최대지연 시간은 41.4 ps, 42.1 ps에서 20.1 ps, 20.8 ps 로 50% 이상 감소하였다.