• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.339-342
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• 1998

The various services that a broadband integrated services digital network (B-ISDN) carries, have a wide range of delay, delay jitter and cell loss probability requirements. Design of appropriate control schemes for B-ISDN is an extremely important and challenging problem. In this paper, we proposes a priority control scheme with a delay counter and a cell counter per each class type. The priority control for required service quality is performed with delay/loss factor obstained by comparing window counter with cell counter. The performance of proposed control scheme is estimated by computer simulation.

• 전기의세계
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• v.28 no.3
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• pp.37-50
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• 1979

The time optimal control of dynamic systems with time delay is studied with emphasis on the practical realization of controllers. An extensive survey on various methods of control is included and a result for a time optimal regulator with signle delay in control is presented and simulated on a digital computer.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Journal of Broadcast Engineering
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• v.13 no.2
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• pp.172-178
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• 2008

Orthogonal Frequency Division Multiplexing (OFDM) is one of the most promising technologies for high data rate wireless communications. OFDM has been adopted in wireless standards such as digital audio/video broadcasting. The combination of OFDM and cooperative diversity techniques can provide the diversity gain and/or increased capacity. In this paper, the cooperative coding using cyclic delay diversity (CDD) for multiuser OFDM systems is introduced. To improve the beneficial effects of relays's cooperation, CDD is adopted in cooperative transmission of relays. Simulation results show the bit error rate (BER) for various consideration. The proposed scheme provides improved performance compared to delay.

• Journal of Korea Society of Digital Industry and Information Management
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• v.6 no.1
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• pp.83-90
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• 2010

DTNs (Delay Tolerant Networks) refer to the networks that can support data transmission in the extreme networking situations such as continuous delay and no connectivity between ends. DTMNs (Delay Tolerant Networks) are a specific range of DTNs, and its chief considerations in the process of message delivery in the routing protocol are the transmission delay, improvement of reliability, and reduction of network loading. This article proposes a new LCN (Largest Common Neighbor) routing algorism to improve Spray and Wait routing protocol that prevents the generation of unnecessary packets in a network by letting mobile nodes limit the number of copies of their messages to all nodes to L. Since higher L is distributed to nodes with directivity to the destination node and the maximum number of common neighbor nodes among the mobile nodes based on the directivity information of each node and the maximum number of common neighbor nodes, more efficient node transmission can be realized. In order to verify this proposed algorism, DTN simulator was designed by using ONE simulator. According to the result of this simulation, the suggested algorism can reduce average delay and unnecessary message generation.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.3
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• pp.275-284
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• 2004

This paper discusses how to control the compensation voltages in dynamic voltage restorers (DVR). On analyzing the power circuit of a DVR system, control limitations and control targets are presented for the voltage compensation in DVRs. Based on the preceded power stage analysis, a novel controller for the compensation voltages of DVRs is proposed by a feed forward control scheme. This paper discusses also the time delay problems in the control system of DVRs. Digitally controlled DVR systems normally have control delay at amount of one sampling time of the control system and a half of the switching period of the DVR inverter. The control delay in digital controllers increases the dimension of the system transfer function one degree higher, which makes the control system more complicate and more unstable. This paper proposes a guide line to design the control gain, appropriate output filter parameters and inverter switching frequency for DVRs with digital controllers. Proposed theory is verified by an experimental DVR system with a full digital controller.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.799-804
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• 2012

To converter time information to digital information Time-to-Digital Converter(TDC) is designed by using analog delay elements. To obtain the temperature stable characteristics the circuit is designed and the operation of the designed circuit is confirmed by HSPICE. The characteristics variation of the designed delay element with temperature is from -0.18% to 0.126% compared to room temperature characteristics when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. Time difference is from -0.18% to 0.12% compared to room temperature characteristic when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. The time difference is simulated when the digital output is 15. However the time difference is from -1.09% to 1.28% in the TDC using temperature non-stable analog delay elements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.671-672
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• 2011

Time to digital converter is designed. To obtain the digital signal from time information the analog delay element is used. Because the analog delay element shows more stable characteristics compared to the digital delay element in view point of process variation. The designed circuit has temperature stale characteristics when the range of operating temperature is from $-20^{\circ}C$ to $70^{\circ}C$. The circuit is simulated and confirmed by HSPICE.