• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.529-533
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• 1990

This paper treats the computational time delay issue in designing digital control systems. The computational time delay margin, within which the closed-loop stability is guaranteed, is analyzed using Rouche theorem. A PID control algorithm is proposed for compensating the computational time delay. Finally, the analyzed and the exact computational time delay margins are compared, and the performance of the proposed PID controller is shown through an illustrative example.

• 한국산업정보학회논문지
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• 제17권2호
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• pp.33-43
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• 2012

디지털 사이니지란 멀티미디어 기반의 정보와 광고를 소비자에게 전달하는 스마트 전자 디스플레이 시스템을 일컫는다. 대부분의 디지털 사이니지는 일련의 멀티미디어 콘텐츠를 원격 네트워크 스토리지로부터 로컬 디스크로 다운로드 한 후에 재생을 시작한다. 하지만 모든 콘텐츠를 다운로드 한 후 재생할 경우에 긴 초기 지연시간을 초래한다. 본 논문에서는 디지털 사이니지에서 이러한 초기 지연시간 문제를 정의하고, 주어진 네트워크 대역폭 및 멀티미디어 콘텐츠의 품질과 크기에 따라서 최소한으로 필요한 초기 지연시간을 계산하는 방법을 제시한다. 또한, 디지털 사이니지 상의 다양한 멀티미디어 콘텐츠들을 이용하여 본 제안 기법의 성능을 분석한다.

• Transactions on Control, Automation and Systems Engineering
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• 제2권4호
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• pp.274-284
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• 2000

In this paper, the design methodology of digital fuzzy controller(DFC) for the systems with time-delay is presented and the qualitative effects of the quantizers in digital implementation of a fuzzy controllers are investigated. We propose the fuzzy feed-back controller whose output is delayed with unit sampling period and period and predicted. the analysis and the design problem considering time-delay become very easy because the proposed controller is syncronized with the sampling time. The stabilization problem of the digital fuzzy system with time-delay is solved by linear matrix inequality(LMI) theory. Furthermore, we analyze the stability of the quantized fuzzy system. Our results prove that when quantization os taken into account, one only has convergence to some small neighborhood about origin. We develop a fuzzy control system for backing up a computer-simulated truck-trailer with the consideration of time-delay and quantization effect. By using the proposed method, we analyze the quantization effect to the system and design a DFC which guarantees the stability of the control system in the presence of time-delay.

• Progress in Superconductivity
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• 제9권2호
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• 전력전자학회논문지
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• 제21권1호
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• pp.49-57
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• 2016

A modular multilevel converter is widely adapted for a high-voltage direct current power transmission system. This study proposes a design methodology for a novel digital control that mitigates the negative effects caused by time delay, including communication transport delay for a modular multilevel converter. The modeling and negative effect of time delay are analyzed theoretically in a frequency domain, and its compensation methodology based on an inverse model is described fully with practical considerations. The proposed methodology is verified through several simulation results using a modular 21-level converter system.

• 한국전자파학회논문지
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• 제22권6호
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• pp.577-583
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• 2011

레이더의 설계에 있어 레이더 성능 평가는 중요한 단계 중 하나이다. 그러나 조우 표적을 가지고 성능 시험을 수행하는 데는 시간 및 비용과 같은 제약점이 따르기 때문에 가상의 표적을 모의할 수 있는 장치가 개발되어 레이더 성능 평가에 사용된다. 가상의 표적 모의 장치는 광 지연 선로 및 DRFM(Digital RF Memory)을 이용하여 구현되어 왔으나, 모의 거리 및 사용 용도의 차이로 인한 시험 시나리오 구현 등에 있어 제약점을 가지고 있다. 이에 본 논문에서는 임의의 레이더 송신 신호에 대하여 정밀 거리 모의가 가능하며, 시험 시나리오 구현이 용이한 레이더 반사 신호 모의 장치 개발을 목표로 구현된 디지털 시간 지연 모듈에 대하여 기술하였다. 개발된 디지털 시간 지연 모듈은 펄스 인식 및 지연 간격 검출 방법을 적용하여 왜곡이 없는 시간 지연을 모의하다. 자체시험 결과를 통하여 성능 입증하였으며 그 결과에 대하여 기술한다.

• 한국항해항만학회지
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• 제26권3호
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• pp.295-302
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• 2002

현재의 디지털 통신시스템은 매우 다양한 디지털 변조방식을 채택하고 있다. 이러한 통신시스템에서는 인접채널에 대한 간섭을 최대한 줄이기 위해서 필연적으로 선형 전력증폭기를 요한다. 선형 전력증폭기는 매우 다양한데 그 중에서 전방궤환 전력증폭기는 구조상 광대역이면서 선형화 정도가 매우 우수하다. 전방궤환 전력중폭기에 사용되는 지연선로의 손실로 인하여 전체효율이 감소한다. 본 논문에서는 이러한 지연선로를 손실이 매우 작은 지연필터를 사용함으로써 효율과 선형성을 동시에 개선하였다. 측정된 결과 ACLR이 약 17.43dB 개선되었으며 이것은 지연필터를 사용함으로써 2.54dB 더 개선되었음을 나타낸다.

• 한국통신학회논문지
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• 제22권11호
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• pp.2401-2408
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• 1997

The measured pulse shapes provided in the given data package demonstrated pulse distortions due to laser speckle. the distorted pulse shapes were carefully analyzed, modeled, and then applied to the DTTL(Digital-data Transition Tracking Loop)[1] bit synchronizer simulator to measure the mean time delay and its delay variation performance. The result showed that the maximum mean time delay variation with the modeled data was 12.5% when window size equals 1. All the data given were located within this modeled boundary and the maximum eman time delay variation was 7% in this case. The mean time delay variation was known to be smaller by reducing the window size [2][5][6]. The mitigated delay variation was 2.5% in the modeled case and 1.4% in the data set given when the windown size equals 0.1. With the digital DTTL insteal of analog DTTL, similar results was obtained.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 추계학술대회 논문집
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• pp.36-40
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• 2003

On analyzing the power circuit of a DVR system, control limitations and control targets are presented for the voltage compensation in DVRs. The control delay in digital controllers increases the dimension of the system transfer function one degree higher which makes the control system more complicate and more unstable. Based on the power stage analysis, a novel controller for the compensation voltages in DVRs is proposed by a feedforward control scheme. Proposed controller works well with the time delay in the digital control system. This paper also proposes a guide line to design the control gain, appropriate output filter parameters and inverter switching frequency for DVRs in digital controllers. Proposed theory is verified by an experimental DVR system with a typical digital controller.