• Journal of IKEEE
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• v.19 no.3
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• pp.342-348
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• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.3
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• pp.120-126
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• 1984

In this paper, there is presented the novel encoder circuit design method in the realization of exponential adaption process on the delta modulation coding of speech signals. The digital implementation has been adapted for the illustration of above, especially using a rate multiplier end a double integration circuit. The use of a double integration of the local decoder included in the ADM encoder in prove the undesirable characteristics which the low switching speed of the ratemultiplier couses the SQNR to decreuse, and the SQNR of the decoding signal by above realization is relatively uniformed in wide range of signal levels. The validity of the above design is verified by laboratory experiments.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Information and Communications Magazine
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• v.14 no.3
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• pp.75-86
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• 1997

This manuscript describes the high level system design for the DCP system. The DCP HS and BS transceivers are composed of five systems, including the RF/IF unit, the Analog Front End(AFE), the baseband modem, the voice codec and the micro-controller. In the following, the core transceiver architecture with the primary functions at these subsystem is described.

• The Journal of the Acoustical Society of Korea
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• v.21 no.3
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• pp.237-244
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• 2002

In this paper we mention the optimization of MPEG-4 VM (Moving Picture Expert Group-4 Verification Model) GA (General Audio) AAC (Advanced Audio Coding) encoder and the design of the decoder for PDA (Personal Digital Assistant) using MPEG-4 VM source. We profiled the VMC source and several optimization methods have applied to those selected functions from the profiling. Intel Pentium III 600 MHz PC, which uses windows 98 as OS, takes about 20 times of encoding time compared to input sample running time, with additional options, and about 10 times without any option. Decoding time on PDA was over 35 seconds for the 17 seconds input sample. After optimization, the encoding time has reduced to 50% and the real time decoding has achieved on PDA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.273-279
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• 2001

This paper describes a design and implementation of ISDN system on a chip which provides ISDN service and used to develop a low-price multimedia communication terminal. This ISDN SOC is an ISDN system control chip which has 32bit RISC processor, and it includes ISDN S interface transceiver, G.711 voice CODEC, PC interface for data communication, ISDN protocol which includes Q.931 call control protocol and internet protocol. It provides good solution to develope ISDN terminal equipment and ISDN terminal adaptor which connected with basic rate interface, because it minimize external peripheral devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2E
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• pp.32-40
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• 1994

It is the purpose of this paper to describe the methods for establishing loudness ratings and talker echo out of transmission quality of ISDN telephone connected to fully digital network. In order to design the desirable loudness ratings and talker echo for ISDN telephone, the model system of digital speech communication for subjective tests is developed. Using this model system, opinion tests which decide the optimal CODEC input level, the range of overall loudness rating, sidetone masking rating and talker echo are performed. From the results of tests, we decided that the loudness ratings are 6 to 8dB for sending, 0 to 2dB for receiving, and 8 to 12dB for sidetone masking rating. And, the terminal coupling loss of TCLw of at least 40dB is necessary to provide echo-free telephone communications to telophone users when the overall loudness rating of ISDN telephone is normalized to 10dB.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.