• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.98-107
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• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.6
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• pp.1087-1098
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• 2023

The rapid advancement of artificial intelligence (AI) technology has led to its proactive utilization across various fields. However, this widespread adoption of AI-based systems has raised concerns about the increasing threat of attacks on these systems. In particular, deep neural networks, commonly used in deep learning, have been found vulnerable to adversarial attacks that intentionally manipulate input data to induce model errors. In this study, we propose a method to protect image classification models from visually imperceptible One-Pixel attacks, where only a single pixel is altered in an image. The proposed defense technique utilizes an autoencoder model to remove potential threat elements from input images before forwarding them to the classification model. Experimental results, using the CIFAR-10 dataset, demonstrate that the autoencoder-based defense approach significantly improves the robustness of pretrained image classification models against One-Pixel attacks, with an average defense rate enhancement of 81.2%, all without the need for modifications to the existing models.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• International Journal of Highway Engineering
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• v.11 no.4
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• pp.59-68
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• 2009

Torsional behavior of concrete pavement slabs due to temperature and moisture effects is constrained by self weight and friction etc, and causes stress as the result. The stress due to humidity variation in the slab is difficult to calculate while that due to temperature variation can easily be calculated by a commercial structural analysis program. Thus, the slab behavior can be predicted more accurately if the humidity effect is converted to equivalent temperature and is used as an input of structural analysis. In this study, a concrete pavement slab was constructed and strains of the slab due to environmental loadings were measured for long-term period. Thermal strains were subtracted from the measured strains by using thermal expansion coefficient of the concrete measured in a laboratory. Shrinkage strains, the remained strains, was supposed as additional thermal strains to calculate imaginary temperature with equivalent effect of the shrinkage by dividing the shrinkage with the thermal expansion coefficient. An existing shrinkage model was modified by considering the self weight and friction to be used in another model which can convert differential shrinkage between top and bottom of the slab to equivalent temperature difference. Addition research efforts on tensile stress reduction according to steady increase in the compressive strains are warranted for more accurate stress calculation.

• Korean Journal of Remote Sensing
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• v.17 no.3
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• pp.231-242
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• 2001

In 2-pass differential SAR interferometry(DInSAR), the topographic phase signature can be removed by using a digital elevation model(DEM) to isolate the contribution of deformation from interferometric phase. This method has an advantage of no unwrapping process, but applicability is limited by precision of the DEM used. The residual phase in 2-pass differential interferogram accounts for error of DEM used in the processing provided that no actual deformation exits. The objective of this paper is a preliminary study to improve DEM precision using low precision DEM and 2-pass DInSAR technique, and we applied the 2-pass DInSAR technique to Asan area. ERS-1/2 tandem complex images and DTED level 0 DEM were used for DInSAR, and the precision of resulting DEM was estimated by a 1:25,000 digital map. The input DEM can be improved by simply adding the DInSAR output to the original low precision DEM. The absolute altitude error of the improved DEM is 9.7m, which is about the half to that of the original DTED level 0 data. And absolute altitude error of the improved DEM is better than that from InSAR technique, 15.8m. This approach has an advantage over the InSAR technique in efficiently reducing layover effects over steep slope region. This study demonstrates that 2-pass DInSAR can also be used to improve DEM precision.

• Journal of electromagnetic engineering and science
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• v.14 no.1
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• pp.1-8
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• 2014

A differential-cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented by 0.18 ${\mu}m$ RF CMOS technology. The loss at the output is minimized by implementing the output transformer on a FR-4 printed circuit board (PCB). The CMOS PA utilizes the $2^{nd}$ harmonic short at the input to enhance the linearity. The measurement was done by the 10MHz bandwidth 16QAM 6.88 dB peak-to-average power ratio long-term evolution (LTE) signal at 1.85 GHz. The ET operation of the CMOS PA with the supply modulator enhances the power-added efficiency (PAE) by 2.5, to 10% over the stand-alone CMOS PA for the LTE signal. The ET PA achieves a PAE of 36.5% and an $ACLR_{E-UTRA}$ of -32.7 dBc at an average output power of 27 dBm.

• International Journal of High-Rise Buildings
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• v.5 no.1
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• pp.1-12
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• 2016

The 1100 foot [335 m] tall Wilshire Grand Center tower under construction in Los Angeles illustrates many key outrigger issues. The tower has a long, narrow floor plan and slender central core. Outrigger braces at three groups of levels in the tower help provide for occupant comfort during windy conditions as well as safety during earthquakes. Because outrigger systems are outside the scope of prescriptive code provisions, Performance Based Design (PBD) using Nonlinear Response History Analysis (NRHA) demonstrated acceptability to the Los Angeles building department and its peer review panel. Buckling Restrained Brace (BRB) diagonals are used at all outrigger levels to provide stable cyclic nonlinear behavior and to limit forces generated at columns, connections and core walls. Each diagonal at the lowest set of outriggers includes four individual BRBs to provide exceptional capacities. The middle outriggers have an unusual 'X-braced Vierendeel' configuration to provide clear hotel corridors. The top outriggers are pre-loaded by jacks to address long-term differential shortening between the concrete core and concrete-filled steel perimeter box columns. The outrigger connection details are complex in order to handle large forces and deformations, but were developed with contractor input to enable practical construction.