• Applied Microscopy
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• 제47권1호
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• pp.55-62
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• 2017

This paper describes experiments aimed at characterizing the behavior of field electron emitters fabricated by coating carbon fibers with epoxylite resin. Polyacrylonitrile carbon fibers of type VPR-19, thermally treated at $2,800^{\circ}C$, were used. Each was initially prepared in a "uncoated" state, by standard electro polishing and cleaning techniques, and was then examined in a scanning electron microscope. The fiber was then baked overnight in a field electron microscope (FEM) vacuum chamber. Current-voltage characteristics and FEM images were recorded on the following day or later. The fiber was then removed from the FEM, coated with resin, "cured" by baking, and replaced in the FEM. After another overnight bake, the FEM characterization measurements were repeated. The coated fibers had significantly better performance than uncoated fibers. This confirms the results of earlier experiments, and is thought to be due in part to the formation of a conducting channel in the resin over layer. For the coated fiber, lower voltages were needed to obtain the same emission current. The coated fibers have current-voltage characteristics that show smoother trends, with greater stability and repeatability. No switch-on phenomena were observed. In addition, the emission images on the phosphor-coated FEM screen were more concentrated, and hence brighter.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.186.1-189
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• 2001

Ferroelectric $Bi_{4-x}$La$_{x}$Ti$_3$O$_{12}$ (BLT)thin films with various compositions(x=0.65, 0.70, 0.75) were prepared on Pt//Ti/SiO$_2$/Si(100) substrate by metal-organic deposition. The electrical and structural characteristics of BLT thin films were investigated to develop ferroelectric thin films for capacitor layers of FRAM. After spin coating, thin films were annealed at $650^{\circ}C$ for 1hour in oxygen atomosphere. Scanning electron micrographs showed uniform surfaces composed of rod-like grains. The $Bi_{4-x}$La$_{x}$Ti$_3$O$_{12}$ (x=0.70) thin film capacitors with a Pt top electrode showed better ferroelectric properties than other films. At the applied voltage of 5V, the dielectric constant($\varepsilon$$_{r}$), dissipation factor(tan$\delta$),remanent polarization(2Pr), and coercive field(2Ec) of the $Bi_{4-x}$La$_{x}$Ti$_3$O$_{12}$ (x=0.70)thin films were about 272.54, 0.059, 32.4 $\mu$C/cm$^2$, 2Ec=119.9kV/cm. Also the capacitor did not show any significant fatigue up to 4.8$\times$10$^{10}$ read/write switching cycles.hing cycles.s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.861-864
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• 2002

Ferroelectric $Bi_{4-x}Nd_xTi_3O_{12}$(BNdT) thin films with the composition(x=0.75) were prepared on pt/Ti/$SiO_2$/Si(100) substrate by metal-organic deposition. The electrical and structural characteristics of BNdT thin films were investigated to develop ferroelectric thin films for capacitor layers of FRAM. After spin coating, thin films were annealed at $650^{\circ}C$ for 1hour in oxygen atmosphere. Scanning electron micrographs showed uniform surfaces composed of rod-like grains. The $Bi_{4-x}Nd_xTi_3O_{12}$(X=0.75) thin film capacitors with a Pt top electrode showed better ferroelectric properties. At the applied voltage of 5V, the dielectric constant$(\varepsilon_r)$, dissipation factor$(tan{\delta})$, remanent polarization(2Pr) and nonvolatile swiching charge of the $Bi_{4-x}Nd_xTi_3O_{12}$(x=0.75)thin films were about 346.7, 0.095, $56{\mu}C/cm^2$ and $38{\mu}C/cm^2$ respectively. Also the capacitor did not show any significant fatigue up to $8{\times}10^{10}$ read/write switching cycles at a frequency of 1MHz.

• 한국진공학회지
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• 제8권4A호
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• pp.425-431
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• 1999

$Pb(Zr_{0.52}, Ti_{0.48})O_3$ (PZT) thick films as an actuating material with conducting oxides, $(La_{0.5}Sr_{0.5}) CoO_3$ (LSCO), have been fabricated by sol-gel method for Optical Micro-Electro-Mechanical System (MEMS) devices, in which PZT/LSCO/SiO2 structures were used. In order to improve the adhesion to LSCO solution in order to enhance the wetting behavior of a water-based LSCO precursor solution and further to improve the adhesion between LSCO and $SiO_2$ layers. PZT films were made using 1-3 propanediol based precursor solution which has a high viscosity and a boiling point appropriate for thick film fabrication. In the precursor solution, Ti-propoxied and Zr-propoxied are partially substituted with acetylacetone to achieve the solution stability while maintaining reactivity. Crack free PZT films (0.8~1$\mu\textrm{m}$) have been successfully fabricated at crystallization temperatures above $700^{\circ}C$. Dielectric constants and dielectric losses of the PZT films were 900~1200and 2~5%, respectively. Piezoelectric constant $d_{33}$ of the PZT films constrained by a substrate were 200pm/V at 100kV/cm.

• 마이크로전자및패키징학회지
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• 제21권4호
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• pp.63-68
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• 2014

For a nanoscale Cu/low-k wafer, inter-layer dielectric (ILD) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects by traditional diamond blade saw process. Sidewall void in sawing street is one of the key factors to bring about cracks and chipping. The aim of this research is to evaluate laser grooving & mechanical sawing parameters to eliminate sidewall void and avoid top-side chipping as well as peeling. An ultra-fast pico-second (ps) laser is applied to groove/singulate the 28-nanometer node wafer with Cu/low-k dielectric. A series of comprehensive parametric study on the recipes of input laser power, repetition rate, grooving speed, defocus amount and street index has been conducted to improve the quality of dicing process. The effects of the laser kerf geometry, grooving edge quality and defects are evaluated by using scanning electron microscopy (SEM) and focused ion beam (FIB). Experimental results have shown that the laser grooving technique is capable to improve the quality and yield issues on Cu/low-k wafer dicing process.

• 한국세라믹학회지
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• 제31권11호
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• pp.1330-1336
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• 1994

Ta2O5 films were deposited on the p-Si(100) substrates by ECR-PECVD and annealed in O2 atmosphere. The thicknesses of Ta2O5/SiO2 layers were measured by an ellipsometer and a cross-sectional TEM. Annealing in O2 atmosphere enhanced the stoichiometry of the Ta2O5 film and reduced the impurity carbon content. Ta2O5 films were crystallized at the annealing temperatures above 75$0^{\circ}C$. The best leakage current characteristics and the maximum dielectric constant of Ta2O5/SiO2 film capacitor were observed in the specimen annealed at $700^{\circ}C$ and 75$0^{\circ}C$, respectively. The flat band voltage of the Al/Ta2O5/SiO2/p-Si MOS capacitor was varied in the range of -0.6~-1.6 V with the annealing temperature. The conduction mechanism in the Ta2O5 film, the variation of the effective oxide charge density with the annealing temperature, and the effective electric field distribution in the Ta2O5/SiO2 double layer were also discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1462-1464
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• 2006

Scaling rules for TFT application devices have led to the necessity of ultra thin dielectric films and high-k dielectric layers. In this paper, The advantages of high concentration of nitrogen in silicon oxide layer deposited by using $N_2O$ in Inductively Coupled Plasma Chemical Vapor Deposition (ICP-CVD) is investigated using X-ray energy dispersive spectroscopy (EDS). We have reported about Ellipsometric measurement, Capacitance - Voltage characterization and processing conditions.

• 한국전기전자재료학회논문지
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• 제14권7호
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.

• 마이크로전자및패키징학회지
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• 제12권3호
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• pp.235-241
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• 2005

Incorporation of solid electrodes frequently involves plasma-based processing. The effect of plasma can influence the physical characteristics, depending on the magnitude in plasma. The undesired feature of plasma-induced damage should be prevented in characterizing the ultra-thin materials, such as ultra-thin films and organic monolayers. The current work at first proves the applicability of a liquid phase electrode in the electrical/dielectric properties through comparative work using Al and Hg on ultrathin $Al_2O_3$ films deposited through atomic layer deposition at low temperature: Two types of metals such as Aluminum (Al) and mercury (Hg) were used as electrodes in $Al_2O_3$ thin films in order to investigate the effect of electrode preparation on the current-voltage characteristics and impedance features as a function of thickness in $Al_2O_3$ film thickness. The success of Hg in $Al_2O_3$ thin films is applied to the AC and DC characterization of the organic monolayers obtained using the Langmuir-Blodgett method. From the DC current-voltage characteristics, the diode-like response is found to originate from the bulk response of the organic materials, evidenced by the fact and the capacitance is inversely related to the absolute thickness of organic layers.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권1호
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• pp.27-32
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• 2003

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.