• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.586-591
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• 2004

We studied the dependence of hot-tarrier-induced degradation characteristics on nitrogen concentration in NO(Nitrided-Oxide) gate of nMOS, under ac and dc stresses. The $\Delta$V$_{t}$ and $\Delta$G$_{m}$ dependence of nitrogen concentration were observed, We observed that device degradation was suppressed significantly when the nitrogen concentration in the gate was increased. Compared to $N_2$O oxynitride, NO oxynitride gate devices show a smaller sensitivity to ac stress frequency. Results suggest that the improved at-hot carrier immunity of the device with NO gate may be due to the significantly suppressed interface state generation and neutral trap generation during stress.ess.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.34-41
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• 1999

In this paper, hot carrier induced performance degradation of peripheral circuits in memory devices such as static type imput buffer, latch type imput buffer and sense amplifier circuit has been measured and analyzed. The used design and fabrication of the peripheral circuits were $0.8 {\mu}m$ standard CMOS process. The analysis method is to find out which device is most significantly degraded in test circuits by using spice simulation, and then to characterize the correlation between device and circuit performance degradation. From the result of the performance degradation of static type input buffer, the trip point was increased due to the transconductance degradation of NMOS. In the case of latch type input buffer, there was a time delay due to the transconductance degradation of NMOS device. Finally, hot carrier induced the decrease of half-Vcc voltage and the increased of sensing voltage in sense amplifier circuits have been measured.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.183-187
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• 2004

The most significant degradation problem of PLED has been described and new buffer layer material aimed for use as HTL in PLED to solve this issue has been studied. This approach has enabled the increase of the green device efficiency (${\sim}$2x) and lifetime (${\sim}$5-6x).

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.326-329
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• 2009

We investigated the degradation of $In_2O_3-Ga_2O_3$-ZnO (IGZO) thin-film transistors (TFTs), which is promising device for driving circuits of nextgeneration displays. We performed the electronic stress test by applying gate and drain voltage. We discussed the degradation mechanism by thermal analysis and device simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.7
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• pp.82-88
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• 1992

This paper presents one of the first comprehensive studies of how hot electron degradation impacts the input offset voltage of a CMOS differential amplifiers. This study utilizes the concept of a virtual source-coupled MOSFET pair in order to evaluate offset voltaged egradation directly from individual device measurement. Next, analytical models are developed to describe the offset voltage degradation. These models are used to examine how hot electron induced offset voltage is affected with the device parameters.

• Transactions on Electrical and Electronic Materials
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• v.13 no.4
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• pp.188-191
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• 2012

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.348-354
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• 2009

It has analyzed that the device degradation by NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOSFETs. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is govern by interface traps density at the silicon/oxide interface. from the relation between the variation of threshold voltage and subthreshold slope, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. Therefore, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1A
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• pp.80-86
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• 2010

This work has been measured and analyzed the device degradation of NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOS transistors of gate channel length 0.13 [${\mu}m$]. From the relation between the variation of threshold voltage and subthreshold slop by NBTI stress, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. As a results, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress parameters of nanoscale CMOS communication circuit design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.21-29
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• 2004

Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.719-722
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• 2003

This work investigates the device degradation p-channel PD SOI devices at various applied voltages as well as stress temperatures with respect to Body-Contact SOI (BC-SOI) and Floating-Body SOI (FB-SOI) MOSFETs. It is observed that the drain current degradation at the gate voltage of the maximum gate current is more significant in FB-SOI devices than in BC-SOI devices. For a stress at the gate voltage of the maximum gate current and elevated temperature, it is worth noting that the $V_{PT}$ Will be decreased by the amount of the HEIP plus the temperature effects. For a stress at $V_{GS}$ = $V_{DS}$ . the drain current decreases moderately with stress time at room temperature but it decreases significantly at the elevated temperature due to the negative bias temperature instability.