• Title/Summary/Keyword: Design of a Block

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Applications of Block Pulse Response Circulant Matrix and its Singular Value Decomposition to MIMO Control and Identification

  • Lee, Kwang-Soon;Won, Wan-Gyun
    • International Journal of Control, Automation, and Systems
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    • v.5 no.5
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    • pp.508-514
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    • 2007
  • Properties and potential applications of the block pulse response circulant matrix (PRCM) and its singular value decomposition (SVD) are investigated in relation to MIMO control and identification. The SVD of the PRCM is found to provide complete directional as well as frequency decomposition of a MIMO system in a real matrix form. Three examples were considered: design of MIMO FIR controller, design of robust reduced-order model predictive controller, and input design for MIMO identification. The examples manifested the effectiveness and usefulness of the PRCM in the design of MIMO control and identification. irculant matrix, SVD, MIMO control, identification.

Decomposition Characteristics of Fungicides(Benomyl) using a Design of Experiment(DOE) in an E-beam Process and Acute Toxicity Assessment (전자빔 공정에서 실험계획법을 이용한 살균제 Benomyl의 제거특성 및 독성평가)

  • Yu, Seung-Ho;Cho, Il-Hyoung;Chang, Soon-Woong;Lee, Si-Jin;Chun, Suk-Young;Kim, Han-Lae
    • Journal of Korean Society of Environmental Engineers
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    • v.30 no.9
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    • pp.955-960
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    • 2008
  • We investigated and estimated at the characteristics of decomposition and mineralization of benomyl using a design of experiment(DOE) based on the general factorial design in an E-beam process, and also the main factors(variables) with benomyl concentration(X$_1$) and E-beam irradiation(X$_2$) which consisted of 5 levels in each factor was set up to estimate the prediction model and the optimization conditions. At frist, the benomyl in all treatment combinations except 17 and 18 trials was almost degraded and the difference in the decomposition of benomyl in the 3 blocks was not significant(p > 0.05, one-way ANOVA). However, the % of benomyl mineralization was 46%(block 1), 36.7%(block 2) and 22%(block 3) and showed the significant difference of the % that between each block(p < 0.05). The linear regression equations of benomyl mineralization in each block were also estimated as followed; block 1(Y$_1$ = 0.024X$_1$ + 34.1(R$^2$ = 0.929)), block 2(Y$_2$ = 0.026X$_2$ + 23.1(R$^2$ = 0.976)) and block 3(Y$_3$ = 0.034X$_3$ + 6.2(R$^2$ = 0.98)). The normality of benomyl mineralization obtained from Anderson-Darling test in all treatment conditions was satisfied(p > 0.05). The results of prediction model and optimization point using the canonical analysis in order to obtain the optimal operation conditions were Y = 39.96 - 9.36X$_1$ + 0.03X$_2$ - 10.67X$_1{^2}$ - 0.001X$_2{^2}$ + 0.011X$_1$X$_2$(R$^2$ = 96.3%, Adjusted R$^2$ = 94.8%) and 57.3% at 0.55 mg/L and 950 Gy, respectively. A Microtox test using V. fischeri showed that the toxicity, expressed as the inhibition(%), was reduced almost completely after an E-beam irradiation, whereas the inhibition(%) for 0.5 mg/L, 1 mg/L and 1.5 mg/L was 10.25%, 20.14% and 26.2% in the initial reactions in the absence of an E-beam illumination.

A New ASIC Design of Digital Hologram Generation Circuit for 12×12 Block (12×12 블록의 디지털 홀로그램 생성 회로의 ASIC 설계)

  • Lee, Yoon-Hyuk;Kim, Dong-Wook;Seo, Young-Ho
    • Journal of Broadcast Engineering
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    • v.21 no.6
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    • pp.944-956
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    • 2016
  • In this paper, we propose a new hardware architecture to generate computer-generated holograms based on the block based calculation method and implement a VLSI (very large scaled integrated circuit) in ASIC (application specific integrated circuit) environment. The proposed hardware has a structure that can produce a part of a hologram in the unit of a block in parallel. After calculating a block of a hologram by using an object point, the calculation is repeated to all object points and intermediate results from them are accumulated to produce a final block of a hologram. Through this structure, we can make various size of holograms with the optimized memory access in real-time operation. The proposed hardware was implemented in the Hynix 0.18um CMOS technology of Magna chip Inc. and has 876,608 gate counts. It can generate complex holograms unlike the previous researches and stably operate in the clock frequency of 200MHz.

Efficient Hardware Design of Hash Processor Supporting SHA-3 and SHAKE256 Algorithms (SHA-3과 SHAKE256 알고리듬을 지원하는 해쉬 프로세서의 하드웨어 설계)

  • Choi, Byeong-Yoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.6
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    • pp.1075-1082
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    • 2017
  • This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

The Design of Beam Forming Module for Active Phased Array Antenna System (능동위상배열안테나용 수신 빔 성형모듈 설계)

  • 정영배;엄순영;전순익;채종석
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2002.11a
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    • pp.118-122
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    • 2002
  • This paper is concerned with the design of the beam forming module that is a key unit of the active phased array antenna(APAA) system for mobile satellite communications. This module includes two blocks for main signal and tracking signal. Main signal block has the role of transmitting input signal from phased away antenna to tracking signal block. And, tracking signal block executes main roles, beam forming of tracking signal and electronic beam control. The several electrical performances of this module, phase characteristics and linear gain, etc., agreed with specifications needed for APAA, and for more clear verification of the performances, the satellite communication test of the APAA including the modules was accomplished in the outdoors.

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Compressive Stress Distribution of Concrete for Performance-Based Design Code (성능 중심 설계기준을 위한 콘크리트 압축응력 분포)

  • Lee, Jae-Hoon;Lim, Kang-Sup;Hwang, Do-Kyu
    • Journal of the Korea Concrete Institute
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    • v.23 no.3
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    • pp.365-376
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    • 2011
  • The current Concrete Structural Design Code (2007) prescribe the equivalent rectangular stress block of the ACI 318 Building Code as concrete compressive stress distribution for design of concrete structures. The rectangular stress block may be enough for flexural strength calculation, but realistic stress-strain relationship is required for performance verification at selected limit state in performance-based design. Moreover, the ACI rectangular stress block provides non-conservative flexural strength for high strength concrete columns. Therefore a new stress distribution model is required for development of performance-based design code. This paper proposes a concrete compressive stress-strain distribution model for design and performance verification. The proposed model has a parabolic-rectangular shape, which is adopted by Eurocode 2 and Japanese Code (JSCE). It was developed by investigation of experimental test results conducted by the authors and other researchers. The test results cover high strength concrete as well as normal strength concrete. The stress distribution parameters of the proposed models are compared to those of the ACI 318 Building Code, Eurocode 2, Japanese Code (JSCE) and Canadian Code (CSA) as well as the test results.

Low Power Cryptographic Design based on Circuit Size Reduction (회로 크기 축소를 기반으로 하는 저 전력 암호 설계)

  • You, Young-Gap;Kim, Seung-Youl;Kim, Yong-Dae;Park, Jin-Sub
    • The Journal of the Korea Contents Association
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    • v.7 no.2
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    • pp.92-99
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    • 2007
  • This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

A Study on the Edge Construction of CMM Data Using a Method of Mean Curvature Block (평균곡률 구간법을 이용한 CMM 데이터의 경계 형성 연구)

  • Chang, Byoung-Chun;Kim, Dae-Il;Oh, Seok-Hyung
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.9 no.1
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    • pp.74-80
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    • 2010
  • The purpose of reverse engineering design using 3D measurement data is an accurate reconstruction of real body. In oder to accomplish this object, it is important that creating exact extracting edges should be studying out first of all. This study used edge-based method to find out edge point from the measuring point data. The characteristics are analysed using the mean curvature block method on the fitting NURBS curve and defined edges through block removal condition. The results showed that only using the NURBS curve of maximum curvature analysis to define correct edge of real geometry is limited, but this segmentation approach provides simplified necessary condition for edge classification, and an effectiveness to classify a straight line, curves and fillets etc.

Design of Sigma Filter in DCT Domain and its application (DCT영역에서의 시그마 필터설계와 응용)

  • Kim, Myoung-Ho;Eom, Min-Young;Choe, Yoon-Sik
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.178-180
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    • 2004
  • In this work, we propose new method of sigma filtering for efficient filtering and preserving edge regions in DCT Domain. In block-based image compression technique, the image is first divided into non-overlapping $8{\times}8$ blocks. Then, the two-dimensional DCT is computed for each $8{\times}8$ block. Once the DCT coefficients are obtained, they are quantized using a specific quantization table. Quantization of the DCT coefficients is a lossy process, and in this step, noise is added. In this work, we combine IDCT matrix and filter matrix to a new matrix to simplify filtering process to remove noise after IDCT in spatial domain, for each $8{\times}8$ DCT coefficient block, we determine whether this block is edge or homogeneous region. If this block is edge region, we divide this $8{\times}8$ block into four $4{\times}4$ sub-blocks, and do filtering process for sub-blocks which is homogeneous region. By this process, we can remove blocking artifacts efficiently preserving edge regions at the same time.

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Design and Implementation of MODA Allocation Scheme based on Analysis of Block Cleaning Cost (블록 클리닝 비용 분석에 기초한 MODA할당 정책 설계 및 구현)

  • Baek, Seung-Jae;Choi, Jong-Moo
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.11
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    • pp.599-609
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    • 2007
  • Due to the restrictions of Flash memory such as overwrite limitation and write/erase operational unit differences, block cleaning is required in Flash memory based file systems and known as a key factor on the performance of file systems. In this paper, we identify three parameters, namely utilization, invalidity and uniformity, and analyze how the parameters affect the cost of block cleaning. The analysis show that as uniformity degrades, the cost of block cleaning increases drastically. To overcome this problem, we design a new modification-aware(MODA) page allocation scheme that strives to keep uniformity high by separating frequently-updating data from infrequently-updating data. Real implementation experiments conducted on an embedded system show that the MODA scheme can actually enhance uniformity of Flash memory, which consequently leads to reduce the cost of block cleaning with an average of 123%, compared to the traditional sequential allocation scheme that is used in YAFFS.