• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2679-2689
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• 1997

In this paper, a multimedia authoring system using temporal/spatial synchronization manager is designed and implemented to support easy and efficient generation of multimedia title. For this goal, a flowchart-oriented logic generator which represents a title author's design intent into a practical title composition logic without extra translation process, and a logic interpreter which translate and implement the generated title logic, are designed. Furthermore, a temporal/spatial synchronization manager which manages temporal/spatial synchronization information between media data for multimedia representation, is designed. Especially, a temporal specification model and MRL, a formal language for the model, are designed to synchronize the temporal relation between media objects. The MRL represents a complex temporal relation by simple and clear form, and synchronizes efficiently multimedia representation according to the author's intent. A presentation frame editor which makes coincidence between visible size of representation media and attachment point, is implemented for spatial synchronization.

• Archives of design research
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• v.19 no.4 s.66
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• pp.41-50
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• 2006

It is generally regarded a design system in post-industrial society, which products designed by in-house designers or design consultancy are manufactured in factory and distributed in market for the consumer. Although it is treated an old design system in traditional society, the traces of vernacular design has been remaining in the state of adopted to the periodical needs in these days, also proving the attribute of design culture to constitute human's material environment as well as existing design systems. There were discovered various design artifacts in daily surroundings vary from the established design in several manners, user modifications or manufactures in everyday lives formalized them. It was approached a case study that analyze the changes of artifact configuration and designer/user context and creation process of the non-professional design artifacts, Creativity Template Theory and ACM(Artifact Context Model) have been utilized for the analysis model. From the analysis result, It assume that the everyday artifacts may be ordinary but extra-ordinary including particular ideas and identity represented by everyday designers or users. Beside these characteristics induce the potentiality that reflect on creative motives for the designers or a complementary artifact generator filling up with drawbacks in established design system. The everyday design domain, various explorations and alternatives are made, is seems to be another design practice domain dissimilar to the one in the industry-based design. Moreover it provides an more easily accessability for the approaching user-friendly design, user customization because they conduct the reliable modeling of consumer and end-user. Finally, based on the exploratory study regarding interpretation of context and configuration in the everyday artifacts, new approach for the design process and design education through more detailed cognitive modeling of everyday designers will be a further study.

• Journal of Korean Ophthalmic Optics Society
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• v.19 no.3
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• pp.339-344
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• 2014

Purpose: This study relates to the development of the day and night scope using the reflecting surface of a BS (beam splitting) prism. Methods: We have placed the LCD panel and the dot reticle generator to the top and bottom of the reflecting surface of the BS prism, and have placed a reflector, which is designed to doublet type, in the front of the BS prism. Doing so, we have developed a new type of day and night scope, which is able to image the virtual image of dot reticle from the dot reticle generator to the direction of the observer, to make the observer survey the peripheral information of the outside target by 1x magnification, and to make the observer survey the image of the LCD panel directly. Results: We could develope a new type of day and night scope, which has the function of night scope as thermal image display device at night time and the function of day scope as dot sight at day time, by letting the reflective surface of the BS prism have the role of dot sight which reflects the dot reticle and have the role of reflective optical system by which the observer surveys the night thermal image displayed in LCD panel. Conclusions: In this study, we have developed the new type of day and night scope which is able to play the role of the day or night scope selectively, combining the existing dot sight and the existing night scope by using the BS prism. By doing so, we could design and fabricate the new type of day and night scope with the BS prism which can further increase the rapidity of firing and provide more convenience in the mounting of a firearm than the detachable combination of an existing dot sight and an existing night scope.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.403-411
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• 2020

Since the analog circuit of the beta ray sensor circuit for the true random number generator and the power and ground line used in the comparator circuit are shared with each other, the power generated by the digital switching of the comparator circuit and the voltage drop at the ground line was the cause of the decreasein the output signal voltage drop at the analog circuit including CSA (Charge Sensitive Amplifier). Therefore, in this paper, the output signal voltage of the analog circuit including the CSAcircuit is reduced by separating the power and ground line used in the comparator circuit, which is the source of digital switching noise, from the power and ground line of the analog circuit. In addition, in the voltage-to-voltage converter circuit that converts VREF (=1.195V) voltage to VREF_VCOM and VREF_VTHR voltage, there was a problem that the VREF_VCOM and VREF_VTHR voltages decrease because the driving current flowing through each current mirror varies due to channel length modulation effect at a high voltage VDD of 5.5V when the drain voltage of the PMOS current mirror is different when driving the IREF through the PMOS current mirror. Therefore, in this paper, since the PMOS diode is added to the PMOS current mirror of the voltage-to-voltage converter circuit, the voltages of VREF_VCOM and VREF_VTHR do not go down at a high voltage of 5.5V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.338-347
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• 2021

In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.240-240
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• 2011

The first neutral beam injector (NBI-1) has been developed for the Korea Superconducting Tokamak Advanced Research (KSTAR) tokamak. A first long pulse ion source (LPIS-1) has been installed on the NBI-1 for an auxiliary heating and current drive of KSTAR core plasmas. Performance of ion and neutral beam extractions in the LPIS-1 was investigated initially on the KSTAR NBI-1 system, prior to the neutral beam injection into the main plasmas. The ion source consists of a JAEA magnetic bucket plasma generator with multi-pole cusp fields and a set of KAERI prototype-III tetrode accelerators with circular apertures. The inner volume of plasma generator and accelerator column in the LPIS-1 is approximately 123 liters. Final design requirements for the ion source were a 120 kV/ 65 A deuterium beam and a 300 s pulse length. The extraction of ion beams was initiated by the formation of arc plasmas in the LPIS-1, called as an arc-beam extraction method. A stable ion beam extraction of LPIS-1 has been achieved up to an 100 kV/42 A for a 4 s pulse length and an 80 kV/25 A for a 14 s pulse length. Optimum beam perveance of 1.21 microperv has been found at an accelerating voltage of 80 kV. Neutralization efficiency has been measured by using a water flow calorimetry (WFC) method of calorimeter and an operation of bending magnet. The full-energy species of ion beams have been detected by using the diagnostic method of optical multichannel analyzer (OMA). An arc efficiency of the LPIS was 0.6~1.1 A/kW depending on the operating conditions of arc discharge.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.421-422
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• 2011

The first part is about development of a liquid target for a neutron source, which is designed to overcome many of the limitations of traditional beam-target neutron generators by utilizing a liquid target neutron source. One of the most critical aspects of the beam-target neutron generator is the target integrity under the beam exposure. A liquid target can be a good solution to overcome damage to the target such as target erosion and depletion of hydrogen isotopes in the active layer, especially for the one operating at high neutron fluxes with no need for water cooling. There is no inherent target lifetime for the liquid target neutron generator when used with continuous refreshment of the target surface exposed to the energetic beam. In this work, liquid target containing hydrogen has been developed and tested in vacuum environment. Potentially, liquid targets could allow a point neutron source whose spatial extension is on the order of 1 to $10{\mu}m$. And the second is about the vacuum ultraviolet (VUV) spectrometer which is designed as a five-channel spectral system for ITER main plasma measurement. To develop and verify the design, a two-channel prototype system was fabricated with No. 3 (14.4 nm~31.8 nm) and No. 4 (29.0 nm~60.0 nm) among the five channels. For test of the prototype system, a hollow cathode lamp is used as a light source. The system is composed of a collimating mirror to collect the light from source to slit, and two holographic diffraction gratings with toroidal geometry to diffract and also to collimate the light from the common slit to detectors. The two gratings are positioned at different optical distances and heights as designed. To study the appropriate detector for ITER VUV system, two different electronic detectors of the back-illuminated charge coupled device and the micro-channel plate electron multiplier were installed and the performance has been investigated and compared in the same experimental conditions. The overall system performance was verified by measuring the spectrums.

• Journal of IKEEE
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• v.13 no.4
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• pp.63-68
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• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.2
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• pp.197-204
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• 2013

A method was developed for analyzing the radiation heat transfer from the duct burner flame to the heat exchanger in a heat recovery steam generator (HRSG) in order to supplement the existing thermal design process. The burner flame and the heat exchanger were considered to be imaginary planes, and the flame temperature, surface, and emissivity were simplified using an engineering approach. Three analysis cases in which the duct burner position and fuel were changed were considered. The calculated flame radiative heat transfer and local flux on the heating surface were compared with those of 3-atomic gas radiation and convection. In all analysis cases, heat transfer by 3-atomic gas radiation was very small. The ratio of the flame radiative heat transfer to the convection heat transfer on the heating surface was estimated to be as high as 8-41%. Moreover, the local heat flux on the heating surface centerline was dominated by flame radiative heat flux.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.55-65
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• 2000

In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.