• Title/Summary/Keyword: Delayed feed-forward path

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Third order Sigma-Delta Modulator with Delayed Feed-forward Path for Low-power Operation (저전력 동작을 위한 지연된 피드-포워드 경로를 갖는 3차 시그마-델타 변조기)

  • Lee, Minwoong;Lee, Jongyeol
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.10
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    • pp.57-63
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    • 2014
  • This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

Multi-bit Sigma-Delta Modulator for Low Distortion and High-Speed Operation

  • Kim, Yi-Gyeong;Kwon, Jong-Kee
    • ETRI Journal
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    • v.29 no.6
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    • pp.835-837
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    • 2007
  • A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

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Tight Path Following PID Controller for a Vehicle with Time Delay (비행체 시간지연을 고려한 정밀경로추종 PID 제어기법)

  • Rhee, Ihn-Seok;Park, Sang-Hyuk;Lee, Kyoung-Ho
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.39 no.7
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    • pp.618-626
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    • 2011
  • In order to complete missions in a complicated terrain or highly dangerous area, an unmanned aerial vehicle(UAV) needs a fine controller to precisely follow the desired path. A PID controller used for the path following feeds forward path curvature information to the control input to improve the path following performance. High gain for PID controller is necessary to follow path tightly. However the high gain could cause instability or performance degradation when the vehicle has slow dynamics. We present PID controller design method which considers response delay of vehicle as well as path curvature. In order to obtain path curvature the desired path is described as a 3rd order polynomial by applying cubic spline interpolation. We apply the proposed controller to the path following of a UAV which is operated in high altitude and has very slow lateral dynamics. The lateral dynamics are modelled as a first order delayed system in the controller design. Nonlinear simulation shows the UAV with proposed controller follows an arbitrary path very tightly.

Artificial neural network model using ultrasonic test results to predict compressive stress in concrete

  • Ongpeng, Jason;Soberano, Marcus;Oreta, Andres;Hirose, Sohichi
    • Computers and Concrete
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    • v.19 no.1
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    • pp.59-68
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    • 2017
  • This study focused on modeling the behavior of the compressive stress using the average strain and ultrasonic test results in concrete. Feed-forward backpropagation artificial neural network (ANN) models were used to compare four types of concrete mixtures with varying water cement ratio (WC), ordinary concrete (ORC) and concrete with short steel fiber-reinforcement (FRC). Sixteen (16) $150mm{\times}150mm{\times}150mm$ concrete cubes were used; each contained eighteen (18) data sets. Ultrasonic test with pitch-catch configuration was conducted at each loading state to record linear and nonlinear test response with multiple step loads. Statistical Spearman's rank correlation was used to reduce the input parameters. Different types of concrete produced similar top five input parameters that had high correlation to compressive stress: average strain (${\varepsilon}$), fundamental harmonic amplitude (A1), $2^{nd}$ harmonic amplitude (A2), $3^{rd}$ harmonic amplitude (A3), and peak to peak amplitude (PPA). Twenty-eight ANN models were trained, validated and tested. A model was chosen for each WC with the highest Pearson correlation coefficient (R) in testing, and the soundness of the behavior for the input parameters in relation to the compressive stress. The ANN model showed increasing WC produced delayed response to stress at initial stages, abruptly responding after 40%. This was due to the presence of more voids for high water cement ratio that activated Contact Acoustic Nonlinearity (CAN) at the latter stage of the loading path. FRC showed slow response to stress than ORC, indicating the resistance of short steel fiber that delayed stress increase against the loading path.

A 145μW, 87dB SNR, Low Power 3rd order Sigma-Delta Modulator with Op-amp Sharing (연산증폭기 공유 기법을 이용한 145μW, 87dB SNR을 갖는 저전력 3차 Sigma-Delta 변조기)

  • Kim, Jae-Bung;Kim, Ha-Chul;Cho, Seong-Ik
    • Journal of IKEEE
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    • v.19 no.1
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    • pp.87-93
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    • 2015
  • In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.