Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A 145μW, 87dB SNR, Low Power 3rd order Sigma-Delta Modulator with Op-amp Sharing

연산증폭기 공유 기법을 이용한 145μW, 87dB SNR을 갖는 저전력 3차 Sigma-Delta 변조기

  • Kim, Jae-Bung (Dept. of Electronics Engineering, Chonbuk University) ;
  • Kim, Ha-Chul (Dept. of Information and Communication Engineering, Republic of Korea Naval Academy) ;
  • Cho, Seong-Ik (Dept. of Electronics Engineering, Chonbuk University)
  • Received : 2014.11.10
  • Accepted : 2015.03.19
  • Published : 2015.03.31
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Abstract

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

본 논문에서는 디지털 패스가 없는 연산증폭기 공유 기법을 이용한 $145{\mu}W$, 87dB SNR을 갖는 저전력 3차 Sigma-Delta 변조기를 제안한다. 기존 구조는 아날로그와 디지털 패스를 사용한 구조로 첫 번째 적분기의 계수가 작다는 단점을 지연된 피드포워드 패스를 추가하여 개선하였다. 제안한 구조는 디지털 패스를 제거하여 첫 번째 적분기의 계수를 크게 하였고 연상증폭기 공유 기법을 이용하여 전력소모가 기준 구조보다 적다. 전원전압 1.8V, 신호대역폭 20KHz, 샘플링 주파수 2.8224MHz 조건에서 $0.18{\mu}m$ CMOS 공정을 이용하여 제안한 구조의 시뮬레이션한 결과, SNR(Signal to Noise Ratio)은 87dB, 전력소비는 $145{\mu}W$이다.

Keywords

References

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