• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.98-104
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• 2013

This paper presents a WBAN UWB receiver circuit for RTLS(real time location system) and wireless data communication. The UWB receiver is designed to OOK modulation for energy detection. The UWB receiver is designed for sub-sampling techniques using 4bit ADC and DLL.The proposed UWB receiver is designed in $0.18{\mu}m$ CMOS and consumes 61mA with a 1.8V supply voltage. The UWB receiver achieves a sensitivity of -85.7 dBm, a RF front-end gain of 42.1 dB, a noise figure of 3.88 dB and maximum sensing range of 4 meter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.132-139
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• 2002

This paper describes a supply voltage detector and SRAM write driver circuit which dissipates small power. The supply voltage detector generates high signal when supply voltage is higher than reference voltage, but low signal when supply voltage is lower than reference voltage. The write driver utilizes two same-sized drivers to reduce operating current in the write cycle. In the case of lower supply voltage comparing to Vcc, both drivers are active the same as conventional write driver, while in the case of high Vcc only one of two drivers are active so as to deliver the half of the current. As a result of simulation using 0.6${\mu}{\textrm}{m}$ 3.3v/5v, CMOS model parameter, the proposed SRAM scheme shows a 22.6% power reduction and 12.7% PDP reduction at Vcc=3.3V, compared to the conventional one.

• Journal of IKEEE
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• v.23 no.4
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• pp.1257-1264
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• 2019

A 3-GSymbol/s/lane transceiver, which supports the mobile industry processor interface (MIPI) C-physical layer (PHY) specification version 1.1, is proposed. It performs channel mismatch correction to improve the signal integrity that is deteriorated by using three-level signals over three channels. The proposed channel mismatch correction is performed by detecting channel mismatches in the receiver and adjusting the delay times of the transmission data in the transmitter according to the detection result. The channel mismatch detection in the receiver is performed by comparing the phases of the received signals with respect to the pre-determined data pattern transmitted from the transmitter. The proposed MIPI C-PHY receiver is designed using a 65 nm complementary metal-oxide-semiconductor (CMOS) process with 1.2 V supply voltage. The area and power consumption of each transceiver lane are 0.136 ㎟ and 17.4 mW/GSymbol/s, respectively. The proposed channel mismatch correction reduces the time jitter of 88.6 ps caused by the channel mismatch to 34.9 ps.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.301-306
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• 2014

We proposed a new PCB-type 'common-mode current($I_c$) and differential-mode current($I_d$) detector' working for fast detection of $I_c$ and $I_d$ from the differential-mode signaling, with miniaturization effect and possibility of cheaper fabrication. In order to realize this device, we suggest a branch-line-coupler balun having a composite right- and left-handed(CRLH) one-layer microstrip phase-shifting line as compact as roughly ${\lambda}_g/14$. The presented balun obviously is different from the conventional bent-&-folded delay lines or slits on the ground for coupling the lines on the top and bottom dielectrics. As we connect the suggested balun output ports of the differential-mode signal lines via the through-port named U and coupled-port named L, $I_c$ and $I_d$ will appear at port ${\Delta}$ and port ${\Sigma}$ of the present device, in order. The validity of the design scheme is verified by the circuit-and numerical electromagnetic analyses, and the dispersion curve proving the metamaterial characteristics of the geometry. Besides, the examples of the $I_c$ and $I_d$ indicator are observed as the even and odd modes in differential-mode signal feeding. Also, the proposed device is shown to be very compact, compared with the conventional structure.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.721-728
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• 2018

This paper introduces various linear block error correction code and compares performances of the correction circuits. As the risk of errors due to power noise has increased, ECC(: Error Correction Code) has been introduced to prevent the bit error. There are two representatives of ECC structures which are SEC-DED(: Single Error Correction Double Error Detection) and SEC-DED-DAEC(: Double Adjacent Error Correction). According to simulation results, the SEC-DED circuit has advantages of small area and short delay time compared to SEC-DED-DAEC circuits. In case of SED-DED-DAEC, there is no big difference between Dutta's and Pedro's from performance point of view. Therefore, Pedro's code is more efficient than Dutta' code since the correction rate of Pedro's code is higher than that of Dutta's code.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.47-51
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• 2013

A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.

• Nuclear Engineering and Technology
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• v.21 no.4
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• pp.287-293
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• 1989

The purpose of this study was to develop a rapid and effective method of laser-induced fluorescence analysis for thrace amounts of Sm, Eu and Tb in nuclear fuels. The features of the method are the use of the distinct fluorescence wavelengths and the discriminative lifetimes of the respective elements when excited by a pulsed nitrogen laser. Fluorescence signals of the three elements were isolated by adequate selection of the filters or complexing agents (HFA, TTA) or discriminative delay and gate times in the signal processing circuit. It was found that S $m^{+3}$ and E $u^{+3}$ emitted strong fluorescence in the two complexing agent solutions or HFA and TTA. But in the case or T $b^{+3}$, the fluorescence signal was detected only in HFA solution. With respect to the concentrations of S $m^{+3}$, E $u^{+3}$ and T $b^{+3}$, the fluorescence signal intensities gave superior linearities in the range of 5 ppb-10 ppm for S $m^{+3}$, 0.5 ppb-1 ppm for E $u^{+3}$, and 0.1 ppb-300 ppb for T $b^{+3}$, The detection limits obtained were 5 ppb for S $m^{+3}$, 0.1 ppb for E $u^{+3}$, and 0.01 ppb for T $b^{+3}$, respectively.

• Journal of the Korea institute for structural maintenance and inspection
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• v.25 no.4
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• pp.28-36
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• 2021

It is known that buried rebars inside concrete structures are protected from corrosion due to passive layer. It is very important to delay the timing of corrosion or evaluate a detection of corrosion initiation for the purpose of cost-beneficiary service life of a structure. In this study, corrosion monitoring was performed on concrete specimens considering 3 levels of cover depth(60 mm, 45 mm, and 30 mm), W/C(water to cement) ratio(40.0%, 50.0%, and 60.0%) and chloride concentration(0.0%, 3.5%, and 7.0%). OCP(Open Circuit Potential) was measured using agar-based socket type sensors. The OCP measurement showed the consistent behavior where the potential was reduced in wet conditions and it was partially recovered in dry conditions. In the case of 30 mm of cover depth for most W/C ratio cases, the lowest OCP value was measured and rapid OCP recovery was evaluated in increasing cover depth from 30 mm to 45 mm, since cover depth was an effective protection against chloride ion ingress. As the chloride concentration increased, the effect on the cover depth tended to be more dominant than the that of W/C ratio. After additional monitoring and physical evaluation of chloride concentration after specimen dismantling, the proposed system can be improved with increasing reliability of the corrosion monitoring.