• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.918-923
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• 1989

This paper presents a stability condition for Astrom's minimal variance control(MVC) with mismatch of time delay for a SISO ARMAX model containing time delay. The proof of the condition presented here is based on the characteristic equation in the feedback system and its magnitude. This condition, from easy numerical calculation, is able to find the stability of the feedback system without knowing the real time delay.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.12
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• pp.4099-4113
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• 2022

In this paper, we propose improved maximum access delay time, noise variance, and power delay profile (PDP) estimation schemes for orthogonal frequency division multiplexing (OFDM) system in multipath fading channels. To this end, we adopt the approximate maximum likelihood (ML) estimation strategy. For the first step, the log-likelihood function (LLF) of the received OFDM symbols is derived by utilizing only the cyclic redundancy induced by cyclic prefix (CP) without additional information. Then, the set of the initial path powers is sub-optimally obtained to maximize the derived LLF. In the second step, we can select a subset of the initial path power set, i.e. the maximum access delay time, so as to maximize the modified LLF. Through numerical simulations, the benefit of the proposed method is verified by comparison with the existing methods in terms of normalized mean square error, erroneous detection, and good detection probabilities.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of the Korean Institute of Gas
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• v.15 no.3
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• pp.11-18
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• 2011

Ultrasonic guided waves have been widely utilized for long range inspection of structures. Recently, many researchers have paid attention to the tomographic imaging using guided wave for the diagnosis of plate-like structures because group velocity of guided waves is changed by central frequency of transducer and thickness of plate. Currently, Delay and Sum imaging technique and MVDR(Minimum Variance Distortionless Response) imaging technique are performed. So the performance of these two imaging techniques are investigated in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.171-181
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• 1988

In this study, a packet voice/data terminal(PVDT) that services both voice and data in the packet-switched network is implemented. The software structure of the PVDT is designed according to the OSI 7 layer architecture. The discrimination of voice and data is made in the link layer. Voice packets have priority over data packets in order to minimize the transmission delay, and are serviced by a simple protocol so that the overhead arising form the retransmission of packets may be minimized. The hardware structure of the PVDT is divided into five modules; a master control module, a speech proessing module, a speech activity detection module, a telephone interface module, and an input/output interface module. In addition to the hardware implementation, the optimal reconstruction delay of voice packets to reduce the influence of delay variance is analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.4
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• pp.683-690
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• 2018

In this paper, a new signal processing technique is proposed for calibrating gain, phase, delay offsets in array antenna based anti-jamming minimum variance distortionless response (MVDR) global-positioning-system (GPS) receivers. The proposed technique estimates gain, phase and delay offsets across the antennas, and compensates for the offsets based on the estimates. A pilot signal with good correlation characteristics is used for accurate estimation of the gain, phase and delay offsets. Based on the cross-correlation, the delay offset is first estimated and then gain/phase offsets are estimated. For fine delay offset estimation and compensation, an interpolation technique is used, and specifically, the discrete Fourier transform (DFT) is employed for the interpolation technique to reduce the computational complexity. The proposed technique is verified through computer simulation using MATLAB. According to the simulation results, the proposed technique can reduce the gain, phaes and delay offset to 0.01 dB, 0.05 degree, and 0.5 ns, respectively.

• Journal of Navigation and Port Research
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• v.36 no.8
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• pp.637-641
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• 2012

In this paper, the method that reduce a computation time by optimizing computation process is proposed to realize low-power underwater acoustic communication system. At first, dependency of decision delay on tap length of linear equalizer was investigated. Variance is calculated based on this result, and the optimal decision delay bound is estimated. In addition to decide optimal tap length with decision delay, we extracted the MSE(Mean Square Error) graph. From the graph, we obtained variance value of the MSE-decision delay, and estimated the optimum decision delay range from the variance value. Also, using the extracted optimal parameters, we performed a simulation. According to the result, the simulation employing optimal tap length, which is only 40% of maximum tap length, showed a satisfactory performance comparable to simulation employing maximum tap length. We verified that the proposed method has 33% lower tap length than maximal tap length via sea trial.

• International Journal of Human Ecology
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• v.13 no.2
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• pp.1-13
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• 2012

This study examined the effects of academic self-concept (internal factor) and maternal parenting behaviors (external factor) on academic delay of gratification (ADOG). Additionally, models predicting ADOG were compared between Korean and Malaysian children. The participants of this study were 100 Korean third graders and their mothers, and 100 Malaysian third graders and their mothers. The children completed the modified versions of the Academic Delay of Gratification Scale for Children, and Academic Self-Concept Questionnaire. The mothers completed the Parenting Attitude Test. Pearson's correlation tests, independent t-tests, and multiple regression analyses were conducted to test the research hypotheses. The results showed that Korean children reported higher ADOG and academic self-concept scores than that of Malaysian children. Moreover, academic self-concept was found to have a significant positive effect on ADOG among both Korean and Malaysian children. There was no significant gender difference in ADOG for both Korean and Malaysian children. However, the effects of maternal parenting behaviors on ADOG were only detected among the Malaysian children, particularly on Achievement Press. That is, only for the Malaysian children, maternal pressure about academic achievement was found to have a significant positive effect on ADOG. In conclusion, only academic self-concept was found to be a significant predictor explaining the variance in ADOG among Korean children. On the other hand, academic self-concept and maternal parenting behaviors were shown as significant predictors explaining the variance in ADOG among Malaysian children.