• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.08a
• /
• pp.191.2-191.2
• /
• 2013

The negative photoconductivity was frequently observed in some semiconductors. It was known that the origin of the negative photoresponse from ZnO is molecular chemisorption or the charging effect of nanoparticles in bulk matrix. However, the origin of the negative photoresponse of thin film was not still clear. One of possible explanation is due to the deep level trap scheme, which describes the origin of the negative photoresponse via defect state under illumination of light. However, the defect states below Fermi level have high capture rate by Coulomb effect, so that these states are usually filled by electrons if the defect states have donor-like character. Therefore the condition which the defect states located in below Fermi level should be partially filled by electrons make more difficult to understand of mechanism of the negative photoresponse. In this study, n-ZnO/p-Si heterojunction diodes were fabricated by UHV RF magnetron sputter. Then, some diodes show the negative photoresponse under ultra-violet light illumination. The defect state of the ZnO was analyzed by photoluminescence and deep level transient spectroscopy. To interpret the negative photoconductivity, band diagram was simulated by using SCAPS program.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.578-581
• /
• 2001

Silicon wafers using DRAM devices required for high cleaning technology and this cleaning technology was evaluated by defect level or electron life time. This paper examined the correlation of SPV(Surface Photo Voltaic Analyzer) which analyzes diffusion length of minority carriers and DLTS(Deep level Transient Spectroscope) which analyzes defect level.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.88-89
• /
• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• Korean Journal of Materials Research
• /
• v.11 no.1
• /
• pp.55-60
• /
• 2001

The effect of high energy B ion implantation and initial oxygen concentration upon defect formation and gettering of metallic impurities in Czochralski silicon wafer has been studied by applying DLTS( Deep Level Transient Spectroscopy), SIMS(Secondary ton Mass Spectroscopy), BMD (Bulk Micro-Defect) analysis and TEM(Transmission Electron Microscopy). DLTS results show the signal of the deep levels not only in as-implanted samples but also in low and high temperature annealed samples. Vacancy-related deep levels in as- implanted samples were changed to metallic impurities-related deep levels with increase of annealing temperature. In the case of high temperature anneal, by showing the lower deep level concentration with increase of initial oxygen concentration, high initial oxygen concentration seems to be more effective compared with the lower initial oxygen one.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.333.2-333.2
• /
• 2014

RF 스퍼터링 방법을 이용하여 제작된 IGZO 박막 트랜지스터 및 단막을 제조하여 UV처리 유무에 따른 전기적 특성을 평가하였다. IGZO 박막 트랜지스터는 Bottom gate 구조로 제조되었으며 UV처리 이후 전계효과 이동도, 문턱전압 이하 기울기 값등 모든 전기적 특성이 개선된 것을 확인 하였다. 이후 UV처리에 따른 소자의 전기적 특성 개선에 대한 원인을 분석하기위해 물리적, 전기적, 광학적 분석을 실시하였다. XRD분석을 통해 UV처리 유무에 따른 IGZO박막의 물리적 구조 변화를 관찰했지만 IGZO박막은 UV처리 유무에 상관없이 물리적 구조를 갖지 않는 비정질 상태를 보였다. IGZO 박막 트랜지스터의 문턱전압 이하의 기울기 값과을 통하여 반도체 내부에 존재하는 결함의 양을 계산한 결과 UV를 조사하였을 때 결함의 양이 감소하는 결과를 얻었으며 이 결과는 SE를 통해 밴드갭 이하 결함부분을 측정하였을 때와 같은 결과였다. 또한 UV처리 전에는 shallow level defect, deep level defect등의 넓은 준위에서 결함이 발견된 반면 UV처리 이후에는 deep level defect준위는 없어지고 shallow level defect준위 역시 급격하게 감소한 것을 볼 수 있었다. 결과적으로 IGZO 박막의 경우 UV처리를 함에 따라 결함의 양이 감소하여 IGZO박막 트랜지스터의 전계 효과 이동도를 증가 시킬 뿐 아니라 문턱전압 이하 기울기 값을 감소시키는 원인으로 작용하게 된다는 결과를 도출하였다.

• Nuclear Engineering and Technology
• /
• v.55 no.1
• /
• pp.209-214
• /
• 2023

The effect of thermal annealing on defect recovery of in-core neutron-irradiated 4H-SiC was investigated. Au/SiC Schottky diodes were manufactured using a 4H-SiC epitaxial wafer that was neutron-irradiated at the HANARO research reactor. The electrical characteristics of their epitaxial layers were analyzed under various conditions, including different neutron fluences (1.3 × 10¹⁷ and 2.7 × 10¹⁷ neutrons/cm²) and annealing times (up to 2 h at 1700 ℃). Capacity-voltage measurements showed high carrier compensation in the neutron-irradiated samples and a recovery tendency that increased with annealing time. The carrier density could be recovered up to 77% of the bare sample. Deep-level-transient spectroscopy revealed intrinsic defects of 4H-SiC with energy levels 0.47 and 0.68 eV below the conduction-band edge, which were significantly increased by in-core neutron irradiation. A previously unknown defect with a high electron-capture cross-section was discovered at 0.36 eV below the conduction-band edge. All defect concentrations decreased with 1700 ℃ annealing; the decrease was faster when the defect level was shallow.

• Journal of IKEEE
• /
• v.28 no.1
• /
• pp.104-109
• /
• 2024

In this research, we explored the influence of post-annealing atmospheres on the electrical properties of Ga₂O₃/SiC heterojunction diodes. We fabricated Ga₂O₃/SiC heterojunction diodes by RF sputtering and after the fabrication the post-annealing in various gas atmospheres was performed. We measured the changes in deep-level defects using Deep Level Transient Spectroscopy (DLTS) and we conducted an electrical characteristic of J-V measurement and Hall measurement to analyzed the effects of annealing atmosphere on Ga₂O₃/SiC heterojunction diode. In the N₂ annealed devices, the highest on-state current was measured as 3.06 × 10^-2 A/cm^2, and an increase in carrier concentration of 3.8 × 10¹⁴ cm^-3 was observed. This confirms that the variations in deep level defects due to the post-annealing atmosphere can influence the electrical properties.

• Proceeding of EDISON Challenge
• /
• 2017.03a
• /
• pp.404-411
• /
• 2017

이 논문에서는 2차원 화합물 반도체인 Indium Selenide monolayer의 효과적인 도펀트 원소를 탐색해보았다. 총 4가지 종류의 원소를 도핑시켜 계산을 했다. In 자리에 Mg과 Sn을 도핑시켜 각각 p-type과 n-type으로 만들고 Se 자리에 As과 Br을 도핑시켜 각각 p-type과 n-type으로 만들었다. 변화한 성질을 알아보기 위해 전자 구조를 분석하고 band structure와 DOS를 살펴보았다. P-type 같은 경우, Mg doped InSe는 shallow defect level이 생겨 좋은 반도체로 쓰일 수 있지만 As을 도핑한 InSe는 deep defect states가 생겼다. VBM에서 약 0.67 eV만큼 떨어져있는데 이 수치는 실험값과 비슷한 값이다. N-type 경우에는 Sn doped InSe는 deep defect states가 생겼고, CBM 아래로 약 0.08eV만큼 defect가 생긴 것이 실험값과 비슷하다. Br doped InSe는 Sn doped InSe보다 안정적인 n형 반도체가 될 수 있다.

• Journal of Information Processing Systems
• /
• v.19 no.6
• /
• pp.745-755
• /
• 2023

The wire rope is an indispensable production machinery in coal mines. It is the main force-bearing equipment of the underground traction system. Accurate detection of wire rope defects and positions exerts an exceedingly crucial role in safe production. The existing defect detection solutions exhibit some deficiencies pertaining to the flexibility, accuracy and real-time performance of wire rope defect detection. To solve the aforementioned problems, this study utilizes the camera to sample the wire rope before the well entry, and proposes an object based on YOLOv5. The surface small-defect detection model realizes the accurate detection of small defects outside the wire rope. The transfer learning method is also introduced to enhance the model accuracy of small sample training. Herein, the enhanced YOLOv5 algorithm effectively enhances the accuracy of target detection and solves the defect detection problem of wire rope utilized in mine, and somewhat avoids accidents occasioned by wire rope damage. After a large number of experiments, it is revealed that in the task of wire rope defect detection, the average correctness rate and the average accuracy rate of the model are significantly enhanced with those before the modification, and that the detection speed can be maintained at a real-time level.

• Journal of IKEEE
• /
• v.26 no.1
• /
• pp.50-55
• /
• 2022

SiC is a power semiconductor with a wide bandgap, high insulation failure strength, and thermal conductivity, but many deep-level defects. Defects that appear in SiC can be divided into two categories, defects that appear in physical properties and interface traps that appear at interfaces. In this paper, Z_1/2 trap concentration 0 ~ 9×10¹⁴ cm^-3 reported at room temperature (300 K) is applied to SiC substrates and epi layer to investigate turn-on characteristics. As the trap concentration increased, the current density, Shockley-read-Hall (SRH), and Auger recombination decreased, and Ron increased by about 550% from 0.004 to 0.022 mohm.