• Proceedings of the Materials Research Society of Korea Conference
• /
• 2009.05a
• /
• pp.37.2-37.2
• /
• 2009

다이렉트 프린팅 방식에 대한 수요가 높아지면서 마이크로 노즐에 대한 수요도 높아지고 있다. 마이크로 노즐은 Nano particle deposition system (NPDS)에서 가장 중요한 부분으로 금속이나 세라믹 분말을 음속으로 가속시키는 역할을 한다. 또한 마이크로 노즐은 마이크로 스페이스 셔틀과 주사바늘이 없는 약물 주사 시스템 등의 많은 분야에서 사용 가능하다. 이러한 마이크로 노즐은 대부분 기계적 절삭법을 이용하여 알루미늄으로 만들어져왔다. 하지만 알루미늄으로 만들어진 마이크로 노즐은 경도가 낮아 세라믹 나노 입자를 적층하는 것에 적절치 못하며 사용가능한 수명이 짧다는 단점을 가지고 있다. 또한 가장 큰 단점으로 노즐목을 1mm이하로 제작하는 것이 어렵다는 것이다. 따라서 본 연구에서는 Si wafer를 Deep RIE 방식을 이용하여 3차원적으로 제작하였다. Deep RIE 방식 중 BOSCH process를 이용하였다. 이렇게 만들어진 마이크로 노즐은 다이렉트 프린팅 방식중 하나인 NPDS에 적용하였다. Si wafer로 만들어진 마이크로 노즐이 적용된 NPDS를 이용하여 graphite 분말을 가속하여 적층 실험을 실시하였다 이와 함께 전산 유체 역학(CFD)를 이용하여 마이크로 노즐일 이용한 초음속 가속 가능 여부를 판단하였다. 전산 유체 역학은 유한 요소법을 이용하여 유체의 거동을 시뮬레이션을 통하여 예측하는 것으로 마이크로 노즐 내에서 유체의 흐름을 예상할 수 있다. 실제 실험의 결과와 전산 유체 역학을 이용한 시뮬레이션 결과dml 비교 분석을 실시하였다.

• Journal of the Korean Vacuum Society
• /
• v.13 no.1
• /
• pp.34-38
• /
• 2004

Hot embossing master is indispensable for the fabrication of polymeric optical waveguides using hot embossing technology. Sidewall roughness of silicon master is directly related to optical loss of optical waveguides In this paper, a silicon master was fabricated by using a deep-RIE process. Additionally, thermal oxidation followed by oxide removal was carried out to minimize etched Si sidewall roughness. Thermal oxidation and oxide removal were performed with $H_2O_2$ atmosphere at $1050^{\circ}C$ and $NH_4$F:HF=6:l BOE, respectively, for the oxide thickness of 400$\AA$, 1000$\AA$, 3000$\AA$, 4500$\AA$, 5600$\AA$ and 6200$\AA$. The sidewall roughness was characterized by SEM and SPM-AFH measurements. We found that the roughness was improved from 12nm (RMS) to 6nm (RMS) for the scalloped sidewall and from 162nm (RMS) to 39nm (RMS) for the vertical striation sidewall, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.14 no.1
• /
• pp.1-5
• /
• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Proceedings of the KIEE Conference
• /
• 1998.11c
• /
• pp.723-725
• /
• 1998

STI CMP process are substituting gradually for LOCOS(Local Oxidation of Silicon) process to be available below sub-0.5um technology and to get planarized. The other hand, STI CMP process(especially STI CMP with RIE etch back process) has some kinds of defect like Nitride residue, Torn Oxide defect, etc. In this paper, we studied how to reduce Torn Oxide defects after STI CMP with RIE etch back process. Although Torn Oxide defects which occur on Oxide on Trench area is not deep and not sever, Torn oxide defects on Moat area is sometimes very deep and makes the yield loss. We did test on pattern wafers witch go through Trench process, APCVD process, and RIE etch back process by using an REC 472 polisher, IC1000/SUV A4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the root causes of torn oxide defects.

• KIEE International Transactions on Electrophysics and Applications
• /
• v.4C no.4
• /
• pp.149-154
• /
• 2004

This paper presents a silicon probe tip for vertical probe card application. The silicon probe tip was fabricated using MEMS technology such as porous silicon micromachining and deep- RIE (reactive ion etching). The thickness of the silicon epitaxial layers was 5 ${\mu}{\textrm}{m}$ and 7 ${\mu}{\textrm}{m}$, respectively. The width and length were 40 ${\mu}{\textrm}{m}$ and 600 ${\mu}{\textrm}{m}$, respectively. The probe structure was a multilayered structure and was composed of Au/Ni-Cr/Si$_3$N$_4$/n-epi layers. The height of the curled probe tip was measured as a function of the annealing temperature and time. Resistance characteristics of the probe tip were measured using a touchdown test.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2002.06a
• /
• pp.172-173
• /
• 2002

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2006.10a
• /
• pp.198-201
• /
• 2006

In this paper, we fabricated drag force type and pressure difference type gas flow sensor with dry etching technology which used Deep RIE(reactive ion etching) and etching stop technology which used SOI(silicon-on-insulator). we fabricated four kinds of sensor, which are cantilever, paddle type, diaphragm, and diaphragm with orifice type. Both cantilever and paddle type flow sensors have similar sensitivity as 0.03mV/V kPa. Sensitivity of the fabricated diaphragm and diaphragm with orifice type sensor were relatively high as about 3.5mV/V kPa, 1.5mV/V kPa respectively.

• Journal of the Semiconductor & Display Technology
• /
• v.7 no.1
• /
• pp.1-5
• /
• 2008

In this paper, we fabricated pressure difference type gas flow sensor using only dry etching technology by ICP-RIE(inductive coupled plasma reactive ion etching). The sensor's structure consists of a common shear stress type piezoresistive pressure sensor with an orifice fabricated in the middle of the sensor diaphragm. Generally, structure like diaphragm is fabricated by wet etching technology using TMAH, but we fabricated diaphragm by only dry etching using ICP-RIE. To equalize the thickness of diaphragm we applied insulator($SiO_2$) layer of SOI(Si/$SiO_2$/Si-sub) wafer as delay layer of dry etching. Size of fabricated diaphragm is $1000{\times}1000{\times}7\;{\mu}m^3$ and overall chip $3000{\times}3000{\times}7\;{\mu}m^3$. We measured the variation of output voltage toward the change of gas pressure to analyze characteristics of the fabricated sensor. Sensitivity of fabricated sensor was relatively high as about 1.5mV/V kPa at 1kPa full-scale. Nonlinearity was below 0.5%F.S. Over-pressure range of the fabricated sensor is 100kPa or more.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.1
• /
• pp.1-6
• /
• 2011

We have developed the process of forming one body S-type cantilever probe in the recessed trench for fine-pitched MEMS probe card. The probe (cantilever beam and pyramid tip) was formed using Deep RIE etching and wet etching. The pyramid tip was formed by the wet etching using KOH and TMAH. The process of forming the curved probe was also developed by the wet etching. Therefore, the fabricated probe is applicable for the probe card for DRAM, Flash memory and RF devices tests and probe tip for IC test socket.

• Journal of the Korean Society for Precision Engineering
• /
• v.26 no.12
• /
• pp.32-40
• /
• 2009