Journal of the Korean Society for Precision Engineering (한국정밀공학회지)

Korean Society for Precision Engineering (한국정밀공학회)
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DRIE Technology for TSV Fabrication

TSV 형성을 위한 DRIE 기술

  • 백규하 (한국전자통신연구원 RFID/USN 연구부) ;
  • 김동표 (한국전자통신연구원 RFID/USN 연구부) ;
  • 박건석 (한국전자통신연구원 RFID/USN 연구부) ;
  • 강진영 (한국전자통신연구원 RFID/USN 연구부) ;
  • 이기준 (충남대학교 전자공학과) ;
  • 도이미 (한국전자통신연구원 RFID/USN 연구부)
  • Published : 2009.12.01
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References

  1. Kittla, J. A., Opsomera, K., Popovicia, M., Menoua, N., Kaczera, B., Wanga, X. P., Adelmanna, C., Pawlaka, M. A., Tomidaa, K., Rothschilda, A., Govoreanua, B., Degraevea, R., Schaekersa, M., Zahida, M., Delabiea, A., Meersschauta, J., Polspoela, W., Climaa, S., Pourtoisa, G, Knaepenb, W., Detavernierb, C., Afanas'evc, V. V., Blombergd, T., Pierreuxe, D., Swertse, J., Fischere, P., Maese, J. W., Mangerf, D., Vandervorsta, W., Conarda, T., Franqueta, A., Faviaa, P., Bendera, H., Brijsa, B., Van Elshochta, S., Jurczaka, M., Van Houdta, J. and Woutersa, D. J., "High-k Dielectrics for Future Generation Memory Devices," Microelectronic Engineering, Vol. 86, No. 7-9, pp. 1789-1795, 2009 https://doi.org/10.1016/j.mee.2009.03.045
  2. Wu, Y., Chang, C., Wang, C., Kao, C., Kuo, C. and Ku, A., "Impact of Preanneal Process on Threshold Voltage of MOS Transistors for Trench DRAM," Microelectronic Engineering, Vol. 86, No.1, pp. 33-36, 2009 https://doi.org/10.1016/j.mee.2008.08.015
  3. Kim, H., Lee, H. and Maeng, W., "Applications of Atomic Layer Deposition to Nanofabrication and Emerging Nano Devices," Thin Solid Films, Vol. 517, No.8, pp. 2563-2580, 2009 https://doi.org/10.1016/j.tsf.2008.09.007
  4. Samber, M., Grunsven, E., Kums, G., Lugt, A. and Vries, H., "Recent Technology and Material Developments in 3D Packaging and Assembly;" Materials Research Society Symposia Proceedings, Vol. 1112, pp. 189-200, 2009
  5. EMC3D, http://www.emc3d.org/documents/library/marketAnalysis _3 D/Pan%20Pac%203-D%20Technology%20review%20part%20II%20v2.pdf
  6. Charbonnier, J., Henry, D., Jacquet, F., Aventurier, B., Brunet-Manquat, C., Enyedi, G., Bouzaida, N., Lapras, V. and Sinon, N., "Wafer Level Packaging Technology Development for CMOS Image Sensors using Through Silicon Vias," Proceeding of Electronics System Integration Technology Conference, pp. 141-148, 2008
  7. Henry, D., Jacquet, F., Neyret, M., Baillin, X., Enot, T., Lapras, V., Brunet-Manquat, C., Charbonnier, J., Aventurier, B. and SilIon, N., "Through Silicon Vias Technology for CMOS Image Sensors Packaging," Proceeding of Electronic Components and Technology Conference, pp. 556-562, 2008
  8. Ranganathan, N., Ebin, L., Linn, L., Vincent, L., Navas, O., Kripesh, V. and Balasubramanian, N., "Integration of High Aspect Ratio Tapered Silicon Via for Through-Silicon Interconnection," Proceeding of Electronic Components and Technology Conference, pp. 859-865, 2008
  9. http://www.emc3d.org/documents/library/technical/No%201-Semitool-Paul.pdf
  10. Bonkohara, M., Motoyoshi, M., Kamibayashi, K. and Koyanagi, M., "Current and Future Three-Dimensional LSI Integration Technology by "Chip on Chip," "Chip on Wafer," and "Wafer on Wafer"," Materials Research Society Symposia Proceedings, Vol. 970, pp. 35-48, 2007
  11. Li, F., Nicopoulos, C., Richardson, T. and Xie, Y., "Design and Management of 3D Chip Multiprocessors Using Network-in-memory," ACM SIGARCH Computer Architecture News, Vol. 34, No. 2, pp. 130-141, 2006 https://doi.org/10.1145/1150019.1136497
  12. Emma, P. and Kursun, E., "Is 3D Chip Technology the Next Growth Engine for Performance Improvement?," IBM Journal of Research and Development, Vol. 52, No.6, pp. 541-552, 2008
  13. Tezzaron Semiconductors, http://www.tezzaron.com/memory/Overview _30_ DRAM.htm
  14. Motoyoshi, M., Nakamura, H., Bonkohara, M. and Koyanagi, M., "Current and Future 3D-LSI Technology for the Image Sensor Devices," Materials Research Society Symposia Proceedings, Vol. 1112, pp. 25-32, 2009
  15. KOSEN, http://www.kosen21.org/nwebzine/webzine _view.jsp?webzine_seq=39&board_seq=348&data_seq=721, 3-Dimensional Microsystem Packaging
  16. Garrou, P., Bower, C. and Ramm, P., "Handbook of 3D Integration Technology and Applications of 3D Integrated Circuits," Wiley-VCH, pp. 47-91, 2008
  17. Jansen, H., de Boer, M., Unnikrishnan, S., Louwerse, M. and Elwenspoek, M., "Black Silicon Method X: a Review on High Speed and Selective Plasma Etching of Silicon with Profile Control: an In-depth Comparison between Bosch and Cryostat DRIE Processes as a Roadmap to Next Generation Equipment," Journal of Micromechanics and Microengineering, Vol. 19, No.3, Paper No. 033001, 2009
  18. Puech, M., Thevenoud, J., Gruffat, J., Launay, N., Arnal, N. and Godinat, P., "Fabrication of 3D Packaging TSV using DRIE," Symp. on Design, Test, Integration and Packaging of MEMS/MOEMS, pp. 109-114, 2008
  19. Shinde, S., Bauer, S., Massad, J. and Hetherington, D., "Front End of Line Through Silicon Via (TSV) Integration," Mater. Res. Soc. Symp. Proc., Vol. 1112, pp. 151-158, 2009 https://doi.org/10.1557/PROC-1112-E03-02
  20. Chekurov, N., Koskenvuori, M., Airaksinen, V.-M. and Tittonen, I., "Atomic Layer Deposition Enhanced Rapid Dry Fabrication of Micromechanical Devices with Cryogenic Deep Reactive Ion Etching," J. Micromech. Microeng., Vol. 17, No.8, pp. 1731-1736, 2007 https://doi.org/10.1088/0960-1317/17/8/041
  21. Figueroa, R., Spiesshoefer, S., Burkett, S. and Schaper, L., "Control of Sidewall Slope in Silicon Vias Using $SF_6/O_2$ Plasma Etching in a Conventional Reactive Ion Etching Tool," J. Vac. Sci. Technol. B, Vol. 23, No.5, pp. 2226-2231, 2005 https://doi.org/10.1116/1.2041654
  22. Li, R., Lamy, Y., Besling, W., Roozeboom, F. and Sarro, P., "Continuous Deep Reactive Ion Etching of Tapered Via Holes for Three-dimensional Integration," J. Micromech. Microeng., Vol. 18, No. 12, Paper No. 125023, 2008
  23. Mukherjee, P., Kang, M., Zurbuchen, T., Gu, L. and Herrero, F., "Fabrication of High Aspect Ratio Si Nano Gratings with Smooth Sidewalls for a Deep UV-Blocking Particle Filter," J. Vac. Sci. Technol. B, Vol. 25, No.6, pp. 2645-2648, 2007 https://doi.org/10.1116/1.2804612
  24. Tezcan, D., Munck, K., De Pham, N., Luhn, O., Aarts, A., De Moor, P., Baert, K. and Van Hoof, C., "Development of Vertical and Tapered Via Etch for 3D through Wafer Interconnect Technology," Proceeding of Electronics Packaging Technology Conference, pp. 22-28, 2006
  25. Ayon, A., Bayt, R. and Breuer, K., "Deep Reactive Ion Etching: a Promising Technology for Micro- and Nanosatellites," Smart Mater. Struct., Vol. 10, No.6, pp. 1135-1144, 2001 https://doi.org/10.1088/0964-1726/10/6/302
  26. Yeom, J., Wu, Y. and Shannon, M., "Critical Aspect Ratio Dependence in Deep Reactive Ion Etching of Silicon," IEEE International Conference on Transducers Solid-State Sensors, Actuators and Microsystems), Vol. 2, pp. 1631-1634, 2003
  27. Roxhed, N., Griss, P. and Stemme, G., "A Method for Tapered Deep Reactive Ion Etching Using A modified Bosch Process," Journal of Micromechanics and Microengineering, Vol. 17, No.5, pp. 1087-1092, 2007 https://doi.org/10.1088/0960-1317/17/5/031
  28. De Bore, M., Gardeniers, J., Jansen, J., Smulders, E., Gilde, M., Roelofs, G., Sasserath, J. and Elwenspoek M., "Guidelines for Etching Silicon MEMSStructures Using Fluorine High-Density Plasmas at Cryogenic Temperatures," Journal of Microelectromechanical Systems, Vol. 11, No.4, pp. 385-401, 2002 https://doi.org/10.1109/JMEMS.2002.800928