• Title/Summary/Keyword: Data Memory

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Effects of Information Processing Types and Product Ownership on Usage Intention

  • CHOI, Nak-Hwan
    • The Journal of Industrial Distribution & Business
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    • v.12 no.5
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    • pp.47-58
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    • 2021
  • Purpose - Current research aimed at exploring the effect differences between the two types of processing product information such as the imagining and the considering on psychological product ownership which could influence the intent to purchase or use the product, and focused on identifying the interaction effects of activated memory information type and advertising information type on each of the information processing types. Research design, data, and methodology - This study divided the information processing types into imagining and considering, and the consumer's memories were divided into autobiographical or episodic and semantic memory. The advertising information was approached in each of event information being together with the product and product feature information. At empirical study, 2(two types of memory activation: episodic and semantic memory activation) ∗ 2(two types of advertising information: event-focused and product feature-focused advertising information) between-subjects design was used to make four types of questionnaire according to the type of experimental groups. Through the survey platform, 'questionnaire stars' of 'WeChat' in China, 219 questionnaire data were collected for empirical study. The structural equation model in AMOS 26 and Anova were used to verify hypotheses. Results - First, the ownership affected the usage intent positively. Second, the imagining did not affect the psychological ownership but did directly affect the usage intention, and the considering affected the ownership positively. Third, the episodic memory activation positively influenced the imagining and negatively affected the considering, whereas the semantic memory activation positively influenced the considering and negatively affected the imagining. Fourth, event-advertising information increased the effects of the activated episodic memory on the imagining, and feature-advertising information increased the effects of the activated semantic memory on the considering. Conclusions - marketers should develop and advertise their product-related event message to trigger the imaging that directly increase the intent to purchase or use their product, when consumers are under the activation of their episodic memory. And marketers should advertise their product feature-related message to trigger the considering that could induce consumers' ownership for their product to increase the intent to purchase or use their product, when they are under the activation of their semantic memory.

Cycle-accurate NPU Simulator and Performance Evaluation According to Data Access Strategies (Cycle-accurate NPU 시뮬레이터 및 데이터 접근 방식에 따른 NPU 성능평가)

  • Kwon, Guyun;Park, Sangwoo;Suh, Taeweon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.17 no.4
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    • pp.217-228
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    • 2022
  • Currently, there are increasing demands for applying deep neural networks (DNNs) in the embedded domain such as classification and object detection. The DNN processing in embedded domain often requires custom hardware such as NPU for acceleration due to the constraints in power, performance, and area. Processing DNN models requires a large amount of data, and its seamless transfer to NPU is crucial for performance. In this paper, we developed a cycle-accurate NPU simulator to evaluate diverse NPU microarchitectures. In addition, we propose a novel technique for reducing the number of memory accesses when processing convolutional layers in convolutional neural networks (CNNs) on the NPU. The main idea is to reuse data with memory interleaving, which recycles the overlapping data between previous and current input windows. Data memory interleaving makes it possible to quickly read consecutive data in unaligned locations. We implemented the proposed technique to the cycle-accurate NPU simulator and measured the performance with LeNet-5, VGGNet-16, and ResNet-50. The experiment shows up to 2.08x speedup in processing one convolutional layer, compared to the baseline.

Design of Shared Memory Controller Device Driver in Embedded System (임베디드 시스템에서의 공유 메모리 컨트롤러 디바이스 드라이버 설계)

  • Moon, Ji-Hoon;Oh, Jae-Chul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.6
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    • pp.703-709
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    • 2014
  • In the AMP(Asymmetric Multiprocessing) based dual core using core-specific operating system in a single processor system, shared memory method is used to send data between processors in dual core. To used shared memory in different operating systems, there is a problem of needing to solving the issue of message communication and synchronization between the two operations systems. In this paper, separate memory controller was used for data sharing between different processor cores in dual core environment. This controller can designate two slave ports to allow simultaneous access from two processors, and in the case of process data simultaneously by two processors, priority order of slave ports is determined through memory mediator. When sending data from A to B processor, SRAM area was logically separated into 8 pages. It allowed using memory area from multiple processes with the size of 4KByte per page, and control register with the size of 4Byte was used to discern the usability of current page.

데이터 레코드의 Clustering Algorithms

  • 문송천
    • Communications of the Korean Institute of Information Scientists and Engineers
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    • v.5 no.2
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    • pp.90-93
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    • 1987
  • Relatively few papers are known to study the clustering the same kind of data records in a cylinder. In this article, I reviewed the clustering algorithms especially for the cellular list file which have been studied.

The Decline of Memory Performances of Old Adults and its Correlated Factors (노인의 기억수행감소와 관련 요인)

  • Min, Hye Sook
    • Korean Journal of Adult Nursing
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    • v.18 no.3
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    • pp.468-478
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    • 2006
  • Purpose: The purpose of this study were to find out the degree of memory decline and to confirm its correlated factors in old adults. Method: The subjects consisted of 68 old adults over the age 65 who living in Busan. Data were collected by the interview method, using a structured questionnaire and the testing method on the memory performance. Results: The old adults' memory performances declined in tasks of immediately word recall, delayed word recall, and face recognition and increased slightly in word recognition over 2 years. However, there was only significant difference in delayed word recall task. The significant variables to predict memory decline were age, literacy, depression, locus, and strategy. Conclusion: The memory decline of old adults wasn't more serious problem than the perceived one. There needs to be some intervention programs to prevent memory decline for the elderly.

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Page Replacement Algorithm for Improving Performance of Hybrid Main Memory (하이브리드 메인 메모리의 성능 향상을 위한 페이지 교체 기법)

  • Lee, Minhoe;Kang, Dong Hyun;Kim, Junghoon;Eom, Young Ik
    • KIISE Transactions on Computing Practices
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    • v.21 no.1
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    • pp.88-93
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    • 2015
  • In modern computer systems, DRAM is commonly used as main memory due to its low read/write latency and high endurance. However, DRAM is volatile memory that requires periodic power supply (i.e., memory refresh) to sustain the data stored in it. On the other hand, PCM is a promising candidate for replacement of DRAM because it is non-volatile memory, which could sustain the stored data without memory refresh. PCM is also available for byte-addressable access and in-place update. However, PCM is unsuitable for using main memory of a computer system because it has two limitations: high read/write latency and low endurance. To take the advantage of both DRAM and PCM, a hybrid main memory, which consists of DRAM and PCM, has been suggested and actively studied. In this paper, we propose a novel page replacement algorithm for hybrid main memory. To cope with the weaknesses of PCM, our scheme focuses on reducing the number of PCM writes in the hybrid main memory. Experimental results shows that our proposed page replacement algorithm reduces the number of PCM writes by up to 80.5% compared with the other page replacement algorithms.

Memory Hierarchy Optimization in Embedded Systems using On-Chip SRAM (On-Chip SRAM을 이용한 임베디드 시스템 메모리 계층 최적화)

  • Kim, Jung-Won;Kim, Seung-Kyun;Lee, Jae-Jin;Jung, Chang-Hee;Woo, Duk-Kyun
    • Journal of KIISE:Computer Systems and Theory
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    • v.36 no.2
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    • pp.102-110
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    • 2009
  • The memory wall is the growing disparity of speed between CPU and memory outside the CPU chip. An economical solution is a memory hierarchy organized into several levels, such as processor registers, cache, main memory, disk storage. We introduce a novel memory hierarchy optimization technique in Linux based embedded systems using on-chip SRAM for the first time. The optimization technique allocates On-Chip SRAM to the code/data that selected by programmers by using virtual memory systems. Experiments performed with nine applications indicate that the runtime improvements can be achieved by up to 35%, with an average of 14%, and the energy consumption can be reduced by up to 40%, with an average of 15%.

Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices

  • Cha, Jaewon;Kang, Sungho
    • ETRI Journal
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    • v.35 no.1
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    • pp.166-169
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    • 2013
  • In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

A Study on Large Data File Management Using Buffer Cache and Virtual Memory File (가상메모리 화일과 버퍼캐쉬를 이용한 대형 데이타 화일의 처리에 관한 연구)

  • Kim, Byeong-Chul;Shin, Byeong-Seok;Hwang, Hee-Yeung
    • Proceedings of the KIEE Conference
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    • 1991.11a
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    • pp.185-188
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    • 1991
  • In this paper we have designed and implemented a method of using extended memory and hard disk space as a data buffer for application programs to allow handling of large data files in DOS environment. We use a part of the conventional DOS memory as a buffer cache which allows the application program to use extended memory and hard disks transparently. Using buffer cache also allows some speed improvement for the application program. We have also implemented a number of functions to allow easier handling of pointer operations used by application programs.

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Implementation of Maim Memory DBMS for Efficient Transactions based on Embedded System (임베디드 시스템 상에서의 고속 트랜잭션을 위한 메인메모리 기반 데이터베이스 시스템 구현)

  • Kim, Young-Hwan;Son, Jae-Gi;Park, Chang-Won
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.769-770
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    • 2008
  • Mani Memory DataBase(MMDB) system store their data in main physical memory and provide very high-speed access. Conventional database system are optimized for the particular characteristics of disk storage mechanism. Memory resident systems, on the other hand, use different optimizations to structure and organize data, as well as to make it reliable. This paper provides a brief overview on MMDBs and the results after evaluating the performance of our simple MMDB based on Embedded system.

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