• The Journal of the Acoustical Society of Korea
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• v.25 no.4E
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• pp.137-141
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• 2006

This paper presents HE-AAC decoder optimization on TMS320C55x fixed-point DSP core using a DSP-C like FFR code, which provides fast and flexible porting to a DSP core. Our optimization efforts are focused on methodologies that include general optimization methods of FFR code suitable for general DSP or RISC platform in high-level language and software optimization methods in assembly language level. The implementation result requires 48 MIPS and 135 Kbytes memory space to decode 48 Kbps stereo using real Korean S-DMB data.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.96-105
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• 2015

This paper proposes a DSP optimization solution of rain detection and removal algorithm. We propose rain detection and removal algorithms considering camera motion, and also presents optimization results in algorithm level and DSP level. At algorithm level, this paper utilizes a block level binary pattern analysis, and reduces the operation time by using the fast motion estimation algorithm. Also, the algorithm is optimized at DSP level through inter memory optimization, EDMA, and software pipelining for real-time operation. Experiment results show that the proposed algorithm is superior to the other algorithms in terms of visual quality as well as processing speed.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.99-102
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• 2003

Computing environments of Embedded Systems are different from those of desktop computers so that they have resource constraints such as CPU processing, memory capacity, power, and etc.. Thus, when a desktop S/W is ported into embedded systems, optimization should be seriously considered. In this paper, we investigate several S/W optimization techniques to be considered for porting H.263 encoder into a high performance DSP, TMS320C6711. Through experiments, it is found that optimization techniques employed can make a big performance improvement.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.65-70
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• 2008

Digital signal processing (DSP) is the process of taking a signal and performing an algorithm on it to analyze, modify, or better identify that signal.[1] To take advantage of DSP advances, one must have at least a basic understanding of DSP theory along with an understanding of the hardware architecture designed to support these new advances. There are several programming techniques that maximize the efficiency of the DSP hardware, as well as a few fundamental concepts used to implement DSP software. This article introduced some of these underlying functions that are the building blocks of complex signal processing functions, and It will touch on the fundamental concepts of DSP theory and algorithms and also provide an overview of the implementation and optimization of DSP software, and discuss the development of DSP.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.6
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• pp.530-538
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• 2006

DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed features from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10C
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• pp.983-991
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• 2009

While H.264/AVC is in wide use for multimedia applications such as DMB and IPTV service, we have limited usage cases for embedded real-time applications due to its high computational demand. The paper provides judicious guide line for optimization method selection, by presenting the detailed experiments data through the development process of a real time H.264 software encoder on embedded DSP. The experimental analysis includes an intensive profiling analysis, fast algorithm application, optimal memory assignment, and intrinsic-based instruction selection. We have realized a real-time software that encodes CIF resolution videos 15 fps on TMS320DM64x processors.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1820-1825
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• 2005

DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed features from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.454-468
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• 1997

This paper presents a bitwidth optimization algorithm for efficient hardware sharing in digital signal processing system. The proposed algorithm determines the fixed-point representation for each signal through bitwidth optimization to generate the hardware requiring less area. To reduce the operator area, the algorithm partitions the abstract operations in the design description into several groups, such that the operations in the same group can share an operator. The partitioning result are fed to a high-level synthesis system to generate the pipelined fixed-point datapaths. The proposed algorithm has been implemented in SODAS-DSP an automatic synthesis system for fixed-point DSP hardware. Accepting the models of DSP algorithms in schematics, the system automatically generates the fixed-point datapath and controller satisfying the design constraints in area, speed, and SNR(Signal-to-Noise Ratio). Experimental results show that the efficiency of the proposed algorithm by generates the area-efficient DSP hardwares satisfying performance constraints.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.186-189
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• 2019

The technique named CORD is an algorithm that optimizes resources of Data Service Platform(DSP) in real time, and it has been developed for enhancing operability of DSP of Korean e-Navigation Project performed by Hanwha Systems and Ministry of Oceans and Fisheries(MOF) since 2016. It plays a critical role to recognize the state of DSP in early time and handling problems immediately when it occurs logical, physical error in order to make DSP steady state condition, which has something in common with maximizing operability of DSP and seamless maritime service to various ships in the sea. Therefore, as developing a noble technique that makes DSP steady state by diagnosing resource and operation status of DSP as well as by reconfiguring service queue optimally in real time, DSP can have shorter response time and higher chance of providing proper maritime service to ships in voyage.

• The Journal of the Acoustical Society of Korea
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• v.21 no.7
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• pp.648-655
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• 2002

This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.