• Proceedings of the IEEK Conference
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• summer
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• pp.74-76
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• 2004

A Half-VDD Voltage(VHDD) Generator using PMOS pull-up transistor and NMOS pull-down transistor was newly proposed for low-voltage DRAMs. The driving current was increased and the power-on settling time was reduced in the new circuit. The newly proposed VHDD generator worked successfully at VDD at 1.5V and fabricated using 0.18um CMOS twin-well technology.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.177-187
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• 1994

In the design of modern computer systems, the speed gap between the CPUs and DRAMs has been a major concern. To relieve this problem at a low cost, several new DRAM architectures have been proposed. This study is aimed at evaluating quantitatively the impact of the new DRAM architectures (synchronous DRAM. dual-RAS synchronous DRAM, and enhanced DRAM) on the memory system performance. We developed a cache and memory simulator and performed various experiments using the traces generated from four benchmark programs. The simulation results show that the new DRAM architectures offer a better performance than a conventional one by 5~30% in a low cost system and their improvement in a high performance system is less than 1%. However, for resonable multiprogramming workoads, additional performance improvement of about 10~28% is expected in a high performance system while 1~3% in a low cost system.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.549-552
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• 1987

TO INCREASE THE CELL CAPACITANCE Of SMALL GEOMETRY DRAMS. HIGH DIELECTRIC MATERIAL HAS BEEN USED RECENTLY. THE PURPOSE Of THIS WORK IS TO INVESTIGATE THE STRUCTURAL AND ELECTRICAL CHARACTERISTICS Of SiO2/Si3N4/SiO2 STACKED FILM UTILIZING HIGH DIELECTRIC MATERIAL Si3N4(${\epsilon}=7.5$). IN RESULT, THE DIELECTRIC CONSTANT Of STACKED FILM IS 4.0 - 5.0 AND CAPACITANCE AND BREAKDOWN FIELD WERE MORE INCREASED THAN THOSE Of SiO2 FILM.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.649-651
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• 2004

본 논문은 메모리 집적도의 증가로 인해 많이 발생하는 이웃 패턴 감응 고장에 대한 효율적인 테스팅 방법을 제안하고 있다. 기존의 테스팅 방법에서는 비트 단위의 순차적인 셀 어레이 접근으로 인해 결함 검출율과 테스팅 시간에 있어서 문제를 가지고 있다. 이러한 문제들을 본 논문에서는 이웃 패턴 감응 고장을 효율적으로 검출 할 수 있는 타일 방식으로 셀 어레이를 구분하여 이웃 셀의 영역을 제한한다 그리고 기본 셀과 이웃 셀에 필요한 패턴을 병렬로 입출력시킬 수 있는 병렬 접근 디코더와 검출기를 설계함으로써 전체 테스팅 시간을 줄이고 결함 검출율을 높일 수 있는 방법을 제안한다.

• Electronics and Telecommunications Trends
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• v.37 no.1
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• pp.42-52
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• 2022

With the advent of the big data era, the memory capacity required for computing systems is rapidly increasing, especially in High Performance Computing systems. However, the number of DRAMs that can be used in a computing node is limited by the structural limitations of the hardware (for example, CPU specifications). Memory expansion technology has attracted attention as a means of overcoming this limitation. This technology expands the memory capacity by leveraging the external memory connected to the host system through hardware interface such as PCIe and CCIX. In this paper, we present an overview and describe the development trends of the memory expansion technology. We also provide detailed descriptions and use cases of the CCIX that provides higher bandwidth and lower latency than cases of the PCIe.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.132-138
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• 1991

A comparision was made on the influence of BPSG flow temperatures on the electrical properties in submicron CMOS DRAMs containing two BPSG layers. Three different combinations of BPSG flow temperature such as $850^{\circ}C/850^{\circ}C,\;850^{\circ}C/900^{\circ}C,\;and\;900^{\circ}C/900^{\circ}C$ were employed and analyzed in terms of threshold, breakdown and isolation voltage along with sheet resistance and contact resistance. In case of $900^{\circ}C/900^{\circ}C$ flow, the threshold voltage of NMOS was decreased rapidly in channel length less than $0.8\mu\textrm{m}$ with no noticeable change in PMOS and a drastic decrease in breakdown voltages of NMOS and PMOS was observed in channel length less than and equal to $0.7\mu\textrm{m}$ and $0.8\mu\textrm{m}$, respectively. Little changes in threshold and breakdown voltages of NMOS and PMOS, however, were shown down to channel length of $0.6\mu\textrm{m}$ in case of $850^{\circ}C/850^{\circ}C$ flow. The isolation voltage was increased with decreasing BPSG flow temperature. A significant increase in the sheet resistance and contact resistance was noticeable with decreasing BPSG flow temperature from $900^{\circ}C$ to $850^{\circ}C$. All these observations were rationalized in terms of dopant diffusion and activation upon BPSG flow temperature. Some suggestions for improving contact resistance were made.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.4
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• pp.951-959
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• 2017

Under the assumption that there is available some additional information other than plaintext-ciphertext pairs, the security of the RSA cryptosystem has been analyzed by the attack methods such as the side-channel attacks and the lattice-based attacks. Recently, based on the data retention property of the powered-off DRAMs, the so called cold boot attack was proposed in the literature, which is focusing on recovering the various cryptosystems' key from some auxiliary information. This paper is dealing with the problem of recovering the RSA private key with erasures and errors and proposes a new key recovery algorithm which is shown to have better performance than the previous one introduced by Kunihiro et al.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05b
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• pp.16-19
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• 2002

(Ba,Sr)TiO3(BST) thin film is an attractive material for the application in high-density dynamic random access memories (DRAMs) because of the high relative dielectric constant and small variation in dielectric properties with frequency. In this study, (Ba0.6,Sr0.4)TiO3 thin films on Pt/Ti/SiO2/Si substrates were deposited by a sol-gel method and the CF4/Ar inductively coupled plasma (ICP) etching behavior of BST thin films had been investigatedby varying the process parameters such as chamber pressure, ICP power, and substrate bias voltage. To analysis the composition of surface residue following etching BST films etched with different Ar/CF4 gas mixing ratio were investigated using x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometer (SIMS).