• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제54권3호
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• pp.132-138
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• 2005

In this paper a DPDT(Double-Pole Double Through) switch with defected ground structure(DGS) is proposed. The equivalent circuit for the proposed switch structure is derived according to based on equivalent circuit of proposed DGS unit structure. The equivalent circuit parameters of DGS unit are extracted by using the circuit analysis method. The on/off operation of the proposed switch is obtained by varying the capacitance of the varactor diode at the defected ground plane. In the case of ON state, the insertion loss of the fabricated DPDT was shown under 1dB. And in OFF state, we found the rejection characteristic over 20dB at the designed frequency 2.45GHz. The experimental results show excellent insertion loss at on state and isolation at off state.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.557-558
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• 2008

This paper presents the effects of via losses to be connected with an embedded DPDT(Double Pole Double Thru) in a substrate. The substrate consists of two ABF(Ajinomoto Bonding Film) and a Epoxy core. In order to verify and test effects of via, via chains in a substrate using SoP-L process are proposed and measured. Via loss can be calculated as averaging the total via holes. The exact loss of a DPDT switch embedded in substrate are extracted by using the results of via chain and measured data from embedded DPDT. The calculated one via insertion loss is about 0.0005 dB on basis of measured via chains. This result confirms very low loss in via. So the inserti on loss of the embedded switch is confirmed only switch loss as loss is 0.4 dB.

• Transactions on Electrical and Electronic Materials
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• 제18권1호
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• pp.16-20
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• 2017

A RF-MEMS (radio-frequency microelectromechanical-system) based DPDT (double pole double throw) switch for the Ku band has been designed and analyzed for this article. The switch topology is based on the FG-CPW (finite ground-coplanar waveguide) configuration of a microstrip-transmission line. An FEM-based multiphysics solver is used for the evaluation of the spring constant, stress distribution, and pull-in voltage regarding the requirements of the switch-beam unit. The electromagnetic performance of the switch is investigated for a $675{\mu}m$ thick silicon substrate. For the operational frequency of 14.5 GHz, an insertion loss better than -0.3 dB, a return loss better than -40 dB, and input/output- and output-port isolations better than -35 dB are achieved for the switching unit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.511-519
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• 2016

This paper proposes a CMOS 6-bit phase shifter with low RMS phase and amplitude errors for an X-band phased array antenna. The phase shifter combines a switched-path topology for coarse phase states and a switch-filter topology for fine phase states. The coarse phase shifter is composed of phase shifting elements, single-pole double-throw (SPDT), and double-pole double-throw (DPDT) switches. The fine phase shifter uses a switched LC filter. The phase coverage is $354.35^{\circ}$ with an LSB of $5.625^{\circ}$. The RMS phase error is < $6^{\circ}$ and the RMS amplitude error is < 0.45 dB at 8-12 GHz. The measured insertion loss is < 15 dB, and the return losses for input and output are > 13 dB at 8-12 GHz. The input P1dB of the phase shifter achieves > 11 dBm at 8-12 GHz. The current consumption is zero with a 1.2-V supply voltage. The chip size is $1.46{\times}0.83mm^2$, including pads.

• 마이크로전자및패키징학회지
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• 제15권3호
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• pp.53-58
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• 2008

본 연구에서는 상용화된 2.4 GHz 영역대에서 사용되어지는 WiFi용 DPDT(Double Pole Double throw) switch 칩을 laser 비아 가공과 도금 공정을 이용하여 폴리머 기판내에 내장시켜 그 특성을 분석하였으며 통상적으로 실장되는 wire 본딩방식으로 패키징된 기판과 특성차이를 분석 비교하였다. 폴리머는 FR4기판과 아지노 모토사의 ABF(Ajinomoto build up film)를 이용하여 패턴도금법으로 회로를 형성하였다. ABF공정의 최적화를 위해 폴리머의 경화정토를 DSC (Differenntial Scanning Calorimetry) 및 SEM (Scanning Electron microscope)으로 분석하여 경화도에 따라 도금된 구리패턴과의 접착력을 평가하였다. ABF의 가경화도가 $80\sim90%$일 경우 구리층과 최적의 접착강도를 보였으며 진공 열압착공정을 통해 기공(void)없이 칩을 내장할 수 있었다. 내장된 기관과 와이어 본딩된 기판의 측정은 S 파라미터를 이용하여 삽입손실과 반사손실을 비교 분석하였으며 그 결과 삽입손실은 두 경우 유사하게 나타났지만 반사손실의 경우 칩이 내장된 경우 6 GHz 까지 -25 dB 이하로 안정적으로 나오는 것을 확인할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.551-552
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• 2008

This paper presets a results of frequency response in variation of wire bonding length. A gold ball bonding is used as a wire bonding process, and a DPDT(double pole double thru) switch is adapted as a device for test. Wire length is ranged from 442um to 833um and a measured frequency range is from 1 GHz to 6 GHz. Little difference are measured in insertion loss and return loss depending on wire length. Measured S21 and S11 are -0.58 dB and -17.7 dB, respectively. S21 insertion loss is rising up and S11 insertion loss is falling down as the frequency is increased.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.193-197
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• 2013

This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

• ETRI Journal
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• 제35권4호
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• pp.638-643
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• 2013

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.