• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.15-22
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• 2008

The bulk-planer MOSFET has a scaling limitation due to the short channel effect (SCE). The Double-Gate MOSFET (DG-MOSFET) is a next generation device for nanoscale with excellent control of SCE. The quantum effect in lateral direction is important for subthreshold characteristics when the effective channel length of DG-MOSFET is less than 10nm, Also, ballistic transport is setting important. This study shows modeling and design issues of nanoscale DG-MOSFET considering the 2D quantum effect and ballistic transport. We have optimized device characteristics of DG-MOSFET using a proper value of $t_{si}$ underlap and lateral doping gradient.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.16-24
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• 2009

Independent-gate-mode double-gate(IGM-DG) MOSFET overcomes the limitation of 3-terminal device structure, and enables to operate with different voltages for front-gate and back-gate. Therefore, circuit designs becomes not only simple, but also area-efficient due to the controllability of the 4th terminal provided by IGM-DG MOSFETs. In this paper, an RF receiver utilizing IGM-DG MOSFETs is presented and also, the circuit performance is verified by the HSPICE simulations. Besides, the circuit analysis and optimization are performed for various IGM-DG characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.500-510
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• 2013

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.498-501
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator. DG MOSFET have the main gate length of nm and the side gate length of 70nm. Then, we have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nino scale.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.225-232
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• 2009

An analytical compact model for the asymmetric lightly doped Double Gate (DG) MOSFET is presented. The model is developed using the Lambert Function and a 2-dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the net charge and channel current of the DG-MOSFET are derived in section 2. Results for the channel potential and current are compared with 2-D numerical data for a lightly doped DG MOSFET in section 3, showing very good agreement.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1549-1551
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• 2002

현재 게이트 길이가 100nm 이하의 MOSFET 소자를 구현할 때 가장 대두되는 문제인 short channel effect를 억제하는 방법으로 제안된 소자 중 하나가 double gate (DG) silicon-on-insulator (SOI) MOSFET이다. 그러나 DG SOI MOSFET는 두 게이트간의 align과 threshold voltage control 문제가 있다. 본 논문에서는 DG SOI MOSFET에서 이상적으로 게이트가 align된 구조와 back 게이트가 front 게이트보다 긴 non-align된 구조가 subthreshold 동작 영역에서 impact ionization에 미치는 영향에 대해 시뮬레이션을 통하여 비교 분석하였다. 그 결과 게이트가 이상적으로 align된 구조보다 back 게이트가 front 게이트보다 긴 non-align된 구조가 게이트와 드레인이 overlap된 영역에서 impact ionization이 증가하였으며 게이트가 각각 n+ 폴리실리콘과 p+ 폴리실리콘을 가진 소자에서 두 게이트가 같은 work function을 가진 소자보다 높은 impact generation rate을 가짐을 알 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.13-22
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• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET overcomes the limitation of bulk-MOSFET's channel controllability and enables to control the front and back-gate voltages independently. Therefore, circuit designs utilizing the IGM-DG MOSFETs provide the advantage of setting 4-terminal freely, hence achieving not only the performance improvement but also the larger scale integration. This paper presents a 15Gb/s optical receiver with a 1.0V power supply voltage, which consists of a transimpedance amplifier (TIA), a feedforward limiting amplifier (LA), and an output buffer. HSPICE simulations were conducted to confirm the circuit performance, and also to verify the circuit stability issues which may occur from the variations of process and supply voltage.