• Title/Summary/Keyword: DES암호 알고리즘

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Design of modified Feistel structure for high-capacity and high speed achievement (대용량 고속화 수행을 위한 변형된 Feistel 구조 설계에 관한 연구)

  • Lee Seon-Keun;Jung Woo-Yeol
    • Journal of the Korea Society of Computer and Information
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    • v.10 no.3 s.35
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    • pp.183-188
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    • 2005
  • Parallel processing in block cryptographic algorithm is difficult, because Feistel structure that is basis structure of block cryptographic algorithm is sequential processing structure. Therefore this paper changes these sequential processing structure and Feistel structure made parallel processing to be possible. This paper that apply this modified structure designed DES that have parallel Feistel structure. Proposed parallel Feistel structure could prove greatly block cryptographic algorithm's performance such as DES and so on that could not but have trade-off relation the data processing speed and data security interval because block cryptographic algorithm can not use pipeline method because of itself structural problem. Therefore, modified Feistel structure is going to display more superior security function and processing ability of high speed than now in case apply way that is proposed to SEED, AES's Rijndael, Twofish etc. that apply Feistel structure.

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A Study on Data Protection and Performance Analysis by Cryptographic Algorithm in MongoDB Environment (MongoDB 환경에서의 데이터보호 및 암호알고리즘별 성능분석에 대한 연구)

  • Lee, Sun-Ju
    • Proceedings of the Korea Information Processing Society Conference
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    • 2019.05a
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    • pp.133-136
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    • 2019
  • 본 고에서는 약 100 만건의 건강정보를 이용하여 3-Node MongoDB 플랫폼 환경에서 AES, 3DES, ARIA 암호 알고리즘을 이용하여 암호화를 적용하는 방법을 알아본다. 각각의 암호 알고리즘별로 YCSB 성능테스트 툴을 이용하여 다양한 Workload 별로 성능을 테스트를 수행한 뒤, 그 결과를 비교·정리한다.

An Implementation of Authentication and Encryption of Multimedia Conference using H.235 Protocol (H.235 프로토콜에 의한 영상회의의 인증과 암호화 구현)

  • Sim, Gyu-Bok;Lee, Keon-Bae;Seong, Dong-Su
    • The KIPS Transactions:PartC
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    • v.9C no.3
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    • pp.343-350
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    • 2002
  • This paper describes the implementation of H.235 protocol for authentication and media stream encryption of multimedia conference systems. H.235 protocol is recommended by ITU-T for H.323 multimedia conference security protocol to prevent from being eavesdropped and modified by an illegal attacker. The implementation in this paper has used password-based with symmetric encryption authentication. Media streams are encrypted using the Diffie-Hellman key exchange algorithm and symmetric encryption algorithms such as RC2, DES and Triple-DES. Also, 128-bit Advanced Encryption Standard and 128-bit Korean standard SEED algorithms are implemented for the future extension. The implemented authentication and media stream encryption has shown that it is possible to identify terminal users without exposing personal information on networks and to preserve security of multimedia conference. Also, encryption delay time and used memory are not increased even though supporting media stream encryption/decryption, thus the performance of multimedia conference system has not deteriorated.

A Study of Expanded DES for Improving Key Length (키 길이 증가를 위한 확장 DES에 관한 연구)

  • 이상번;남길현
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 1991.11a
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    • pp.95-104
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    • 1991
  • 관용키 암호시스템에서 가장 널리 실용화되어 사용되고 있는 알고리즘은 DES(Data Encryption Standard)이지만, DES의 보안성에 대해서는 공표이래 많은 비판과 논란이 있었으며 그중 56비트의 키로서는 충분한 비도를 제공하기에는 너무나 짧다는 것이 하나의 비판이다. 본 논문에서는 총 112비트의 키가 사용되도록 128비트의 평문을 네 부분으로 나누어 좌우 두개씩 DES알고리즘에 적용하고 좌우측을 교환하는 확장 DES를 제안하고 이를 분석하였다.

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Design of Algorithm for Preventing Decryption of Inaccurate Ciphertext (부정확한 암호문의 복호화를 방지한 알고리즘 설계)

  • 김상복;구명모;김규성
    • Journal of the Korea Computer Industry Society
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    • v.3 no.5
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    • pp.595-604
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    • 2002
  • In this paper, we designed the encryption algorithm which protects ciphertext from deciphering solve the problem that it can pass the incorrect meaning. The algorithm checks the error of ciphertext during deciphering, and then if there are some errors of more than one bit. It stops the deciphering sequence and it doesn't pass any contents to receiver by removing the deciphering contents which was already done. The experiment compared with DES algorithm that is representative algorithm of secret key. As the result of experiment, the part that error bit was included with was deciphered to one that was different from plaintext, but it showed 100% decipher_rate. by the algorithm showed decipher_rate of 0% with deciphering through the error check.

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Design of Validation System for a Crypto-Algorithm Implementation (암호 알고리즘 구현 적합성 평가 시스템 설계)

  • Ha, Kyeoung-Ju;Seo, Chang-Ho;Kim, Dae-Youb
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39B no.4
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    • pp.242-250
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    • 2014
  • Conventional researches of standard tool validating cryptographic algorithm have been studied for the internet environment, for the mobile internet. It is important to develop the validation tool for establishment of interoperability and convenience of users in the information systems. Therefore, this paper presents the validation tool of Elliptic Curve Cryptography algorithm that can test if following X9.62 technology standard specification. The validation tool can be applied all information securities using DES, SEED, AES, SHA-1/256/384/512, RSA-OAEP V2.0, V2.1, ECDSA, ECKCDSA, ECDH, etc. Moreover, we can enhance the precision of validation through several experiments and perform the validation tool in the online environment.

Implementation of the Extended Data Encryption Standard(EDES) (확장된 DES 구현)

  • Han, Seung-Jo;Kim, Pan-Koo
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.6
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    • pp.1565-1575
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    • 1997
  • A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16. This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.

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Differential Cryptanalysis of DES-Like Block Cipher HEA (블록 암호 알고리즘 HEA에 대한 차분분석)

  • 현진수;송정환;강형석
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.10 no.4
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    • pp.107-112
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    • 2000
  • In this paper, we study a security of HEA(Hangul Encryption Algorithm) against differential cryptanalysis. HEA, which is 1,024bits input/output and 56bits key size, has the same structure as DES(Data Encyption Standard) only for Korean characters to be produced in ciphertexts. An encryption algorithm should be developed to meet certain critria such as input/ouput dependencies, correlation, avalanche effects, etc. However HEA uses the same S-Boxes as DES does and just expands the plaintext/ciphertext sizes . We analysize HEA with a differential cryptanalysis and present two results. The number of rounds of HEA has not been determined in a concrete basis of cryptanalysis and we show a chosen plintext attack of 10 round reduced HEA with a diffe- rential cryptanalysis characteristic.

Design and Implementation of Triple-DES Coprocessor for 32-bits Data Bus (32 비트 데이터 버스를 이용한 3-DES Coprocessor의 설계 및 구현)

  • Choi, Hong-Mook;Kim, Yong-Bum;Cho, Hwa-Hyun;Choi, Myung-Ryul
    • Proceedings of the Korea Information Processing Society Conference
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    • 2003.05c
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    • pp.2209-2212
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    • 2003
  • 정보 통신 기술의 발전이 우리 생활을 편리하게 만들고 있지만, 한편으로는 해킹, 도청 등의 부작용이 발생하고 있다. 이러한 부작용을 최소화시키는 결정적인 역할을 하는 분야가 암호 학이다. 현재의 정보 보호 시스템 대부분이 소프트웨어 방식으로 구현되어 있어 암호화 속도 문제 및 해킹에 의한 불법 정보 유출의 위험성이 높은 현실이다. 이러한 점을 해결하기 위해 암호 알고리즘의 하드웨어 구현은 필수적이다. 따라서 본 논문에서는 암호 알고리즘의 속도 및 안전성 문제를 향상시키기 위해 기존에 많이 이용되고 있는 3-DES를 32 비트 데이터 버스를 이용한 하드웨어로 선계 및 구현하여 검증하고 성능 분석을 하였다.

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Design and Implementation of High Speed Encryption Chip of DES using VHDL (VHDL을 이용한 고속 DES 암호칩 설계 및 구현)

  • 한승조
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.8 no.3
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    • pp.79-94
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    • 1998
  • 본 논문에서는 컴퓨터 시스템에서 정보보호를 위해 가장 많이 사용하고 있는 DES(Data Encryption Standard)암호알고리즘을 시스템 설계 기술언어인 VHDL(Vhsic Hardware Description Language)로 설계하고 이것을 칩으로 합성하여 하드웨어에서 차지하는 면적과 속도를 비교 분석하였다. 설계방법에 있어서는 구현하는 방법에 따라 전 라운드 구현형, S-box 공유형 그리고 단일 라운드 반복형 범용성을 갖도록 하여 FPGA로 구현한다. 본 논문에서 구현한 단일 라운드 반복형 설계는 Synopsys의 EDA 툴을 이용하여 시뮬레이션 및 합성을 하였고, Xilinx사의 xdm을 이용하여 XC4052XL 칩에 구현하였다. 그 결과 입력 클록 50MHz상에서 100Mbps의 암,복호화 속도를 갖는 범용성 암호칩을 설계 및 구현한다.