• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권2호
• /
• pp.116-124
• /
• 2001

We implemented POPeye (Probe of Performance ＋ eye), a system analysis simulator to evaluate DRAM performance in a personal computer environment. When running any real-life application programs such as Microsoft Office and Paint Shop Pro on Windows OS, POPeye simulates detailed transactions between a CPU and a memory system. Using this tool, we comparatively analyzed the performance of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM.

• Journal of Astronomy and Space Sciences
• /
• 제33권3호
• /
• pp.229-236
• /
• 2016

We present proton-induced single event effects (SEEs) and γ-ray-induced total ionizing dose (TID) data for 1 Gbit lowpower double data rate synchronous dynamic random access memory (LPDDR SDRAM) fabricated on a 5 μm epitaxial layer (54 nm complementary metal-oxide-semiconductor (CMOS) technology). We compare our radiation tolerance data for LPDDR SDRAM with those of general DDR SDRAM. The data confirms that our devices under test (DUTs) are potential candidates for space flight applications.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
• /
• pp.677-680
• /
• 2009

DC influence between pixel electrode and alignment layer (AL) in in-plane switching mode LCD was analyzed through DC equivalence-circuit equation induction, DC charge-discharge simulation, luminance and residual-DC measurement systems using test patterned (TP) cell. DC discharging rate (DDR) of single layer electrode was faster than that of double layer electrode and DDR of low resistance AL was faster than that of high resistance AL. DC discharging characteristics had a close relation to layer number and resistance between two electrodes.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제10권1호
• /
• pp.45-48
• /
• 2010

An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.

• 한국산학기술학회논문지
• /
• 제11권3호
• /
• pp.853-858
• /
• 2010

본 논문은 알루미늄의 양극산화를 통하여 알루미나(Alumina, $Al_2O_3$)를 형성함으로써 알루미나 및 알루미늄의 적층 구조 DRAM 패키지 기판을 구현하였다. 전송선 기반의 설계를 적용하기 위해 2차원 전자장 시뮬레이션을 수행하였다. 분석 결과를 바탕으로 새로운 기판에 적용할 신호선의 폭 및 간격과 알루미나 두께 등의 설계인자를 최적화하였다. 테스트 패턴 제작 및 측정을 통해 설계인자를 검증하였으며, 이를 바탕으로 설계 룰(Design rule)을 정하고 패키지의 개념 설계 및 상세 설계를 진행하여 DDR2 DRAM 패키지 기판을 성공적으로 제작하였다.

• 대한건축학회논문집:계획계
• /
• 제36권2호
• /
• pp.33-42
• /
• 2020

On October 3, 1990, Germany achieved peaceful reunification by integrating East Germany into West Germany. Since reunification, the region of East Germany had to have a new value standard in extreme social changes such as legal, political, administrative and spatial amid rapid systemic changes. The purpose of this study is to characterize urban policy related to urban change in DDR in the past 30 years after German unification. In particular, this study examined the change of construction law and Städtebauförderung Program as urban policy. The characteristics of Städtebauförderung programs and urban regeneration are in context with their contents. The characteristics of Städtebauförderung program support program are ultimately aimed at resolving imbalances among cities, improving the quality of life of residents and developing cities with future-oriented sustainability.

• 한국콘텐츠학회:학술대회논문집
• /
• 한국콘텐츠학회 2014년도 춘계 종합학술대회 논문집
• /
• pp.459-460
• /
• 2014

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
• /
• pp.819-822
• /
• 2008

모바일 단말의 성능 향상으로 다양한 콘텐츠 서비스에 대한 요구가 증대되고 있다. 하지만 이기종 모바일 단말간의 콘텐츠 표현 성능이 하드웨어나 소프트웨어 등의 측면에서 차이가 있으며 이를 해결하기 위해서는 콘텐츠의 적응화(Adaptation) 과정이 필요하다. 이때 적응화 과정의 기본 정보가 되는 모바일 단말정보를 프로파일(DDL : Device Description Language)로 기술하게 되는데, 이 모바일 단말정보 표현 언어를 효율적으로 관리하기 위한 단말정보 저장소 시스템이 필요하다. 이에 본 논문에서는 모바일 단말정보를 저장하고 콘텐츠 제공 서버의 요청사항에 따라 검색 재조합 등의 과정을 거쳐 최적화된 형태의 프로파일을 제공할 수 있도록 독립된 형태의 단말정보 저장소(Device Description Repository) 시스템을 설계하였다.

• 마이크로전자및패키징학회지
• /
• 제17권4호
• /
• pp.73-76
• /
• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• 전기전자학회논문지
• /
• 제18권4호
• /
• pp.509-516
• /
• 2014

고속동작용 반도체 메모리 제품에 추가된 CRC는 DDR4와 같은 제품에서 데이타의 신뢰도를 증가시킨다. 기존의 CRC 방식은 부가회로 면적이 커고 많은 지연시간이 발생되어, CRC 계산을 위한 내부 타이밍 마진의 부족을 유발한다. 따라서 메모리 제품 설계에서 데이터 입출력 설계에 심각한 문제를 유발한다. 본 논문에서는 오류검출 회로설계를 위한 CRC 코드 방식을 제시하고, 실시간 matrix형 CRC 방법을 제안하였다. 데이터 비트오류 발생시 오류여부를 실시간으로 시스템에 피드백(feedback) 가능하도록 하였다. 제안한 방식은 기존방식(XOR 6단, ATM-8 HEC코드)대비 부가회로 면적을 60% 개선할 수 있으며, XOR 단 지연시간을 33%개선 할 수 있다. 또한 실시간 에러 검출 방식은 전체 데이터 비트(UI0~UI9)에 대해 평균 50% 이상 오류 검출 속도를 향상시켰다.