• Title/Summary/Keyword: DC.Amplifier

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Design and Fabrication of Direct Conversion RF Module using Even Harmonic Mixer for 2-4GHz ISM band (Even Harmonic Mixer를 이용한 2.4GHz ISM band용 Direct Conversion방식의 RF Module 설계 및 제작)

  • 이주갑;윤영섭;최현철
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2001.11a
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    • pp.222-226
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    • 2001
  • In this paper, 2.4GHz RF Module using Even Harmonic Mixer(EHM) was designed and fabricated for Direct conversion(DC) system. By minimizing performance degradation of DC system with DC offset and LO radiation, the capability of minimization and one chip solution in wireless system was proposed. The designed EHM using anti-parallel diode pair represented 9dB conversion loss and about -60dBm 2LO leakage radiation in RF port, and output reflection and reverse transmission characteristic of low noise amplifier was improved. So superior DC offset suppression characteristic is expected. RF Module which consists of EHM, LNA, RF amplifier, Frequency synthesizer and Duplexer was designed and fabricated.

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A DC~7GHz Ultrabroad-Band GaAs MESFET (DC~7GHz 초광대역 GaAs MESFET 증폭기)

  • 윤영철;장익수
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.3
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    • pp.34-42
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    • 1993
  • An analytic approach to wide-band amplification using simplified equivalent MESFET modeling has enabled an ultrabroad-band flat-gain amplifier from DC to microwave. The developed lossy-match ultrabroad-band amplifier operates as a RC coupled circuit in the low-frequency range and lossless impedance matching circuit in the microwave frequency range with gain compensation circuits. The reduced gain caused by external resistors is compensated using 2-stage cascade amplification, and the gain of designed unit is 12.5.+-.1dB from the vicinity of DC to 7GAz. The experimental gain characteristics are good agreement with computer simulated results. The input and output VSWRs are measured under 2:1 over the operating frequency range, and the gain goes down over 15dBrange with various gate bias voltages.

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A Gate-Leakage Insensitive 0.7-V 233-nW ECG Amplifier using Non-Feedback PMOS Pseudo-Resistors in 0.13-μm N-well CMOS

  • Um, Ji-Yong;Sim, Jae-Yoon;Park, Hong-June
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.4
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    • pp.309-315
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    • 2010
  • A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.

An Efficient Bias Circuit of Discrete BJT Component for Hearing Aid (보청기를 위한 개별 BJT 소자의 효과적인 바이어스 회로)

  • 성광수;장형식;현유진
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.6
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    • pp.16-23
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    • 2003
  • In this paper, we propose an efficient bias circuit of discrete BJT component for hearing aid. The collector feedback bias circuit, widely used for the hearing aid, has a resistor for negative feedback. As the resistor affects AC and DC simultaneously, it is quite difficult to adjust amplifier gain without changing DC bias point. The previous bias circuit also has weak point to be oscillated by the positive feedback of power noise if gain of hearing aid is high. In the proposed circuit, we can reduce the two weak points of the previous circuit by adding a resistor to the collector feedback bias circuit between base and power supply which is $\beta$ times target than the collector resistor. Thus. we can change amplifier gain without changing DC bias point, and reduce power noise gain about 18.5% compare to that of tile previous circuit in the simulation.

Design of An Amplifier using DGS Block (DGS 방식 DC Block을 이용한 증폭기의 설계)

  • 이경희;정용채
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.3
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    • pp.432-438
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    • 2001
  • In this paper, after applying Defected Ground Structure(DGS) to DC block, changes of gap and length of λ/4 coupled line are investigated by EM simulation and fabrication. As a result, on condition of the same output with the case using typical DC block, the gap between λ/4 coupled line is widen from 0.1 mm to 0.46 mm by 0.36 mm and the length of λ/4 coupled line gets shorter from 17.7 mm to 13.2 mm by 4.5 mm. Also three type power amplifiers using blocking capacitor, typical DC block and DGS DC block are fabricated and investigated. At first, when S parameter characteristics of each amplifier are considered at frequency band of 3.2 +-0.O5 GHz, every amplifier has similar characteristics of gain and S parameter. Second when the output power of amplifiers is 25 dBm after putting CW signal of 3.2 GHz into three type amplifiers, the difference of dominant signal and 2nd harmonic signal using blocking capacitor, typical DC block and DGS DC block is each -44.83 dBc, -66.84 dBc and -64.33 dBc. Therefore harmonic characteristics of amplifiers using typical DC block and DGS DC block is almost same.

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Design of 20 W Class-E Amplifier Including Protection for Wireless Power Transmission at ISM 13.56 MHz (보호 회로를 포함한 무선 전력 전송용 ISM 13.56 MHz 20 W Class-E 앰프 설계)

  • Nam, Min-Young;Kim, Young-Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.6
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    • pp.613-622
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    • 2013
  • In this paper, an inductive clamping class-E power amplifier has been tested for wireless power transmission at ISM band, 13.56 MHz. The implemented power amplifier is designed to operate stably without destroying power transistor in wireless power transmission system which basically keeps not to align between a transmitting antenna and a receiving antenna. The power amplifier is also designed to enhance harmonic filtering characteristic. The amplifier was tested with a DC supply voltage of 28 V and input power of 25 dBm at 13.56 MHz. The test results show the output power level of 43 dBm, the difference power level between fundamental frequency and second harmonic frequency of more than 55 dBc, the dc current consumption of 830 mA, and the high power-added efficiency of 85 %. Finally, the implemented power amplifier operated normally with 830 mA DC current consumption from 28 V source when the two antennas were aligned, and the power transmission was successful. But when the two antennas were not aligned, its DC current consumption automatically decreased down to 420 mA to protect the switching transistor.

Development of Fully Integrated Broadband MMIC Chip Set Employing CSP(Chip Size Package) for K/Ka Band Applications (CSP(Chip Size Package)를 이용한 완전집적화 K/Ka 밴드 광대역 MMIC Chip Set 개발)

  • Yun Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.1 s.92
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    • pp.102-112
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    • 2005
  • In this work, we developed fully integrated broadband MMIC chip set employing CSP(Chip Size Package) for K/Ka band applications. By utilizing an ACF for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. $STO(SrTi_{3})$ capacitors were employed to integrate the DC biasing components on the MMIC, and LC parallel circuits were employed for DC feed and ESD protection. A pre-matching technique and RC parallel circuit were used to achieve a broadband matching and good stability fer the amplifier MMIC in K/Ka band. The amplifier CSP MMIC exhibited good RF performance over a wide frequency range in K/Ka band. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the K/Ka band.

A 12b 10MS/s CMOS Pipelined ADC Using a Reference Scaling Technique (기준 전압 스케일링을 이용한 12비트 10MS/s CMOS 파이프라인 ADC)

  • Ahn, Gil-Cho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.16-23
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    • 2009
  • A 12b 10MS/s pipelined ADC with low DC gain amplifiers is presented. The pipelined ADC using a reference scaling technique is proposed to compensate the gain error in MDACs due to a low DC gain amplifier. To minimize the performance degradation of the ADC due to amplifier offset, the proposed offset trimming circuit is employed m the first-stage MDAC amplifier. Additional reset switches are used in all MDACs to reduce the memory effect caused by the low DC gain amplifier. The measured differential and integral non-linearities of the prototype ADC with 45dB DC gain amplifiers are less than 0.7LSB and 3.1LSB, respectively. The prototype ADC is fabricated in a $0.35{\mu}m$ CMOS process and achieves 62dB SNDR and 72dB SFDR with 2.4V supply and 10MHz sampling frequency while consuming 19mW power.

A Study on Fabrication and Performance Evaluation of a Driving Amplifier Stage for UHF Transmitter in Digital TV Repeater (DTV 중계기에서의 UHF 전송장치용 구동증폭단의 구현 및 성능평가에 관한 연구)

  • Lee, Young-Sub;Jeon, Joong-Sung
    • Journal of Navigation and Port Research
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    • v.27 no.5
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    • pp.505-511
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    • 2003
  • In this paper, a driving amplifier stage with 1 Watt output has been designed and fabricated, which is operating at UHF band( 470 ∼ 806 MHz) for digital TV repeater. In the driving amplifier stage, preamplifier and 1 Watt unit amplifier are integrated by one electric substrate which is 2.53 in dielectric constant and 0.8 mm thickness. When the driving amplifier stage is flown by bias voltage of 28 V DC and current of 900 mA. it has the gain of more than 53.5 dB. the gain flatness of $\pm$0.5 dB and return loss of less than -15 dB in 470 ∼ 806 MHz. Also, when two signals at 2 MHz frequency interval are input port into the driving amplifier stage with 1 Watt output, it resulted in excellent characteristics to designed specification with showing intermodulation distortion characteristics of more than 48 dBc.